Lines Matching refs:ctx
34 static void gen_spu_event(struct spu_context *ctx, u32 event) in gen_spu_event() argument
40 ch0_cnt = ctx->csa.spu_chnlcnt_RW[0]; in gen_spu_event()
41 ch0_data = ctx->csa.spu_chnldata_RW[0]; in gen_spu_event()
42 ch1_data = ctx->csa.spu_chnldata_RW[1]; in gen_spu_event()
43 ctx->csa.spu_chnldata_RW[0] |= event; in gen_spu_event()
45 ctx->csa.spu_chnlcnt_RW[0] = 1; in gen_spu_event()
49 static int spu_backing_mbox_read(struct spu_context *ctx, u32 * data) in spu_backing_mbox_read() argument
54 spin_lock(&ctx->csa.register_lock); in spu_backing_mbox_read()
55 mbox_stat = ctx->csa.prob.mb_stat_R; in spu_backing_mbox_read()
61 *data = ctx->csa.prob.pu_mb_R; in spu_backing_mbox_read()
62 ctx->csa.prob.mb_stat_R &= ~(0x0000ff); in spu_backing_mbox_read()
63 ctx->csa.spu_chnlcnt_RW[28] = 1; in spu_backing_mbox_read()
64 gen_spu_event(ctx, MFC_PU_MAILBOX_AVAILABLE_EVENT); in spu_backing_mbox_read()
67 spin_unlock(&ctx->csa.register_lock); in spu_backing_mbox_read()
71 static u32 spu_backing_mbox_stat_read(struct spu_context *ctx) in spu_backing_mbox_stat_read() argument
73 return ctx->csa.prob.mb_stat_R; in spu_backing_mbox_stat_read()
76 static __poll_t spu_backing_mbox_stat_poll(struct spu_context *ctx, in spu_backing_mbox_stat_poll() argument
83 spin_lock_irq(&ctx->csa.register_lock); in spu_backing_mbox_stat_poll()
84 stat = ctx->csa.prob.mb_stat_R; in spu_backing_mbox_stat_poll()
95 ctx->csa.priv1.int_stat_class2_RW &= in spu_backing_mbox_stat_poll()
97 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_mbox_stat_poll()
105 ctx->csa.priv1.int_stat_class2_RW &= in spu_backing_mbox_stat_poll()
107 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_mbox_stat_poll()
111 spin_unlock_irq(&ctx->csa.register_lock); in spu_backing_mbox_stat_poll()
115 static int spu_backing_ibox_read(struct spu_context *ctx, u32 * data) in spu_backing_ibox_read() argument
119 spin_lock(&ctx->csa.register_lock); in spu_backing_ibox_read()
120 if (ctx->csa.prob.mb_stat_R & 0xff0000) { in spu_backing_ibox_read()
125 *data = ctx->csa.priv2.puint_mb_R; in spu_backing_ibox_read()
126 ctx->csa.prob.mb_stat_R &= ~(0xff0000); in spu_backing_ibox_read()
127 ctx->csa.spu_chnlcnt_RW[30] = 1; in spu_backing_ibox_read()
128 gen_spu_event(ctx, MFC_PU_INT_MAILBOX_AVAILABLE_EVENT); in spu_backing_ibox_read()
132 ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR; in spu_backing_ibox_read()
135 spin_unlock(&ctx->csa.register_lock); in spu_backing_ibox_read()
139 static int spu_backing_wbox_write(struct spu_context *ctx, u32 data) in spu_backing_wbox_write() argument
143 spin_lock(&ctx->csa.register_lock); in spu_backing_wbox_write()
144 if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) { in spu_backing_wbox_write()
145 int slot = ctx->csa.spu_chnlcnt_RW[29]; in spu_backing_wbox_write()
146 int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8; in spu_backing_wbox_write()
153 ctx->csa.spu_mailbox_data[slot] = data; in spu_backing_wbox_write()
154 ctx->csa.spu_chnlcnt_RW[29] = ++slot; in spu_backing_wbox_write()
155 ctx->csa.prob.mb_stat_R &= ~(0x00ff00); in spu_backing_wbox_write()
156 ctx->csa.prob.mb_stat_R |= (((4 - slot) & 0xff) << 8); in spu_backing_wbox_write()
157 gen_spu_event(ctx, MFC_SPU_MAILBOX_WRITTEN_EVENT); in spu_backing_wbox_write()
162 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_wbox_write()
166 spin_unlock(&ctx->csa.register_lock); in spu_backing_wbox_write()
170 static u32 spu_backing_signal1_read(struct spu_context *ctx) in spu_backing_signal1_read() argument
172 return ctx->csa.spu_chnldata_RW[3]; in spu_backing_signal1_read()
175 static void spu_backing_signal1_write(struct spu_context *ctx, u32 data) in spu_backing_signal1_write() argument
177 spin_lock(&ctx->csa.register_lock); in spu_backing_signal1_write()
178 if (ctx->csa.priv2.spu_cfg_RW & 0x1) in spu_backing_signal1_write()
179 ctx->csa.spu_chnldata_RW[3] |= data; in spu_backing_signal1_write()
181 ctx->csa.spu_chnldata_RW[3] = data; in spu_backing_signal1_write()
182 ctx->csa.spu_chnlcnt_RW[3] = 1; in spu_backing_signal1_write()
183 gen_spu_event(ctx, MFC_SIGNAL_1_EVENT); in spu_backing_signal1_write()
184 spin_unlock(&ctx->csa.register_lock); in spu_backing_signal1_write()
187 static u32 spu_backing_signal2_read(struct spu_context *ctx) in spu_backing_signal2_read() argument
189 return ctx->csa.spu_chnldata_RW[4]; in spu_backing_signal2_read()
192 static void spu_backing_signal2_write(struct spu_context *ctx, u32 data) in spu_backing_signal2_write() argument
194 spin_lock(&ctx->csa.register_lock); in spu_backing_signal2_write()
195 if (ctx->csa.priv2.spu_cfg_RW & 0x2) in spu_backing_signal2_write()
196 ctx->csa.spu_chnldata_RW[4] |= data; in spu_backing_signal2_write()
198 ctx->csa.spu_chnldata_RW[4] = data; in spu_backing_signal2_write()
199 ctx->csa.spu_chnlcnt_RW[4] = 1; in spu_backing_signal2_write()
200 gen_spu_event(ctx, MFC_SIGNAL_2_EVENT); in spu_backing_signal2_write()
201 spin_unlock(&ctx->csa.register_lock); in spu_backing_signal2_write()
204 static void spu_backing_signal1_type_set(struct spu_context *ctx, u64 val) in spu_backing_signal1_type_set() argument
208 spin_lock(&ctx->csa.register_lock); in spu_backing_signal1_type_set()
209 tmp = ctx->csa.priv2.spu_cfg_RW; in spu_backing_signal1_type_set()
214 ctx->csa.priv2.spu_cfg_RW = tmp; in spu_backing_signal1_type_set()
215 spin_unlock(&ctx->csa.register_lock); in spu_backing_signal1_type_set()
218 static u64 spu_backing_signal1_type_get(struct spu_context *ctx) in spu_backing_signal1_type_get() argument
220 return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0); in spu_backing_signal1_type_get()
223 static void spu_backing_signal2_type_set(struct spu_context *ctx, u64 val) in spu_backing_signal2_type_set() argument
227 spin_lock(&ctx->csa.register_lock); in spu_backing_signal2_type_set()
228 tmp = ctx->csa.priv2.spu_cfg_RW; in spu_backing_signal2_type_set()
233 ctx->csa.priv2.spu_cfg_RW = tmp; in spu_backing_signal2_type_set()
234 spin_unlock(&ctx->csa.register_lock); in spu_backing_signal2_type_set()
237 static u64 spu_backing_signal2_type_get(struct spu_context *ctx) in spu_backing_signal2_type_get() argument
239 return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0); in spu_backing_signal2_type_get()
242 static u32 spu_backing_npc_read(struct spu_context *ctx) in spu_backing_npc_read() argument
244 return ctx->csa.prob.spu_npc_RW; in spu_backing_npc_read()
247 static void spu_backing_npc_write(struct spu_context *ctx, u32 val) in spu_backing_npc_write() argument
249 ctx->csa.prob.spu_npc_RW = val; in spu_backing_npc_write()
252 static u32 spu_backing_status_read(struct spu_context *ctx) in spu_backing_status_read() argument
254 return ctx->csa.prob.spu_status_R; in spu_backing_status_read()
257 static char *spu_backing_get_ls(struct spu_context *ctx) in spu_backing_get_ls() argument
259 return ctx->csa.lscsa->ls; in spu_backing_get_ls()
262 static void spu_backing_privcntl_write(struct spu_context *ctx, u64 val) in spu_backing_privcntl_write() argument
264 ctx->csa.priv2.spu_privcntl_RW = val; in spu_backing_privcntl_write()
267 static u32 spu_backing_runcntl_read(struct spu_context *ctx) in spu_backing_runcntl_read() argument
269 return ctx->csa.prob.spu_runcntl_RW; in spu_backing_runcntl_read()
272 static void spu_backing_runcntl_write(struct spu_context *ctx, u32 val) in spu_backing_runcntl_write() argument
274 spin_lock(&ctx->csa.register_lock); in spu_backing_runcntl_write()
275 ctx->csa.prob.spu_runcntl_RW = val; in spu_backing_runcntl_write()
277 ctx->csa.prob.spu_status_R &= in spu_backing_runcntl_write()
283 ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING; in spu_backing_runcntl_write()
285 ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING; in spu_backing_runcntl_write()
287 spin_unlock(&ctx->csa.register_lock); in spu_backing_runcntl_write()
290 static void spu_backing_runcntl_stop(struct spu_context *ctx) in spu_backing_runcntl_stop() argument
292 spu_backing_runcntl_write(ctx, SPU_RUNCNTL_STOP); in spu_backing_runcntl_stop()
295 static void spu_backing_master_start(struct spu_context *ctx) in spu_backing_master_start() argument
297 struct spu_state *csa = &ctx->csa; in spu_backing_master_start()
306 static void spu_backing_master_stop(struct spu_context *ctx) in spu_backing_master_stop() argument
308 struct spu_state *csa = &ctx->csa; in spu_backing_master_stop()
317 static int spu_backing_set_mfc_query(struct spu_context * ctx, u32 mask, in spu_backing_set_mfc_query() argument
320 struct spu_problem_collapsed *prob = &ctx->csa.prob; in spu_backing_set_mfc_query()
323 spin_lock(&ctx->csa.register_lock); in spu_backing_set_mfc_query()
336 ctx->csa.prob.dma_tagstatus_R &= mask; in spu_backing_set_mfc_query()
338 spin_unlock(&ctx->csa.register_lock); in spu_backing_set_mfc_query()
343 static u32 spu_backing_read_mfc_tagstatus(struct spu_context * ctx) in spu_backing_read_mfc_tagstatus() argument
345 return ctx->csa.prob.dma_tagstatus_R; in spu_backing_read_mfc_tagstatus()
348 static u32 spu_backing_get_mfc_free_elements(struct spu_context *ctx) in spu_backing_get_mfc_free_elements() argument
350 return ctx->csa.prob.dma_qstatus_R; in spu_backing_get_mfc_free_elements()
353 static int spu_backing_send_mfc_command(struct spu_context *ctx, in spu_backing_send_mfc_command() argument
358 spin_lock(&ctx->csa.register_lock); in spu_backing_send_mfc_command()
361 spin_unlock(&ctx->csa.register_lock); in spu_backing_send_mfc_command()
366 static void spu_backing_restart_dma(struct spu_context *ctx) in spu_backing_restart_dma() argument
368 ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND; in spu_backing_restart_dma()