Lines Matching refs:phb
523 static void iommu_table_setparms(struct pci_controller *phb, in iommu_table_setparms() argument
532 if (phb->dma_window_base_cur + phb->dma_window_size > SZ_2G) { in iommu_table_setparms()
537 node = phb->dn; in iommu_table_setparms()
546 iommu_table_setparms_common(tbl, phb->bus->number, 0, phb->dma_window_base_cur, in iommu_table_setparms()
547 phb->dma_window_size, IOMMU_PAGE_SHIFT_4K, in iommu_table_setparms()
553 phb->dma_window_base_cur += phb->dma_window_size; in iommu_table_setparms()
563 static void iommu_table_setparms_lpar(struct pci_controller *phb, in iommu_table_setparms_lpar() argument
573 iommu_table_setparms_common(tbl, phb->bus->number, liobn, offset, size, IOMMU_PAGE_SHIFT_4K, NULL, in iommu_table_setparms_lpar()
632 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ in pci_dma_bus_setup_pSeries()
634 while (pci->phb->dma_window_size * children > 0x80000000ul) in pci_dma_bus_setup_pSeries()
635 pci->phb->dma_window_size >>= 1; in pci_dma_bus_setup_pSeries()
637 pci->phb->dma_window_size); in pci_dma_bus_setup_pSeries()
638 pci->phb->dma_window_base_cur = 0; in pci_dma_bus_setup_pSeries()
648 pci->phb->dma_window_size = 0x8000000ul; in pci_dma_bus_setup_pSeries()
649 pci->phb->dma_window_base_cur = 0x8000000ul; in pci_dma_bus_setup_pSeries()
651 pci->table_group = iommu_pseries_alloc_group(pci->phb->node); in pci_dma_bus_setup_pSeries()
654 iommu_table_setparms(pci->phb, dn, tbl); in pci_dma_bus_setup_pSeries()
656 if (!iommu_init_table(tbl, pci->phb->node, 0, 0)) in pci_dma_bus_setup_pSeries()
660 pci->phb->dma_window_size = 0x80000000ul; in pci_dma_bus_setup_pSeries()
661 while (pci->phb->dma_window_size * children > 0x70000000ul) in pci_dma_bus_setup_pSeries()
662 pci->phb->dma_window_size >>= 1; in pci_dma_bus_setup_pSeries()
664 pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size); in pci_dma_bus_setup_pSeries()
737 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node); in pci_dma_bus_setup_pSeriesLP()
739 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, in pci_dma_bus_setup_pSeriesLP()
742 if (!iommu_init_table(tbl, ppci->phb->node, 0, 0)) in pci_dma_bus_setup_pSeriesLP()
765 struct pci_controller *phb = PCI_DN(dn)->phb; in pci_dma_dev_setup_pSeries() local
768 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node); in pci_dma_dev_setup_pSeries()
770 iommu_table_setparms(phb, dn, tbl); in pci_dma_dev_setup_pSeries()
772 if (!iommu_init_table(tbl, phb->node, 0, 0)) in pci_dma_dev_setup_pSeries()
1020 buid = pdn->phb->buid; in query_ddw()
1066 buid = pdn->phb->buid; in create_ddw()
1140 buid = pdn->phb->buid; in reset_dma_window()
1409 for (i = 0; i < ARRAY_SIZE(pci->phb->mem_resources); i++) { in enable_ddw()
1413 if ((pci->phb->mem_resources[i].flags & mask) == IORESOURCE_MEM) { in enable_ddw()
1414 start = pci->phb->mem_resources[i].start; in enable_ddw()
1415 end = pci->phb->mem_resources[i].end; in enable_ddw()
1421 newtbl = iommu_pseries_alloc_table(pci->phb->node); in enable_ddw()
1427 iommu_table_setparms_common(newtbl, pci->phb->bus->number, create.liobn, win_addr, in enable_ddw()
1429 iommu_init_table(newtbl, pci->phb->node, start, end); in enable_ddw()
1524 pci->table_group = iommu_pseries_alloc_group(pci->phb->node); in pci_dma_dev_setup_pSeriesLP()
1526 iommu_table_setparms_lpar(pci->phb, pdn, tbl, in pci_dma_dev_setup_pSeriesLP()
1529 iommu_init_table(tbl, pci->phb->node, 0, 0); in pci_dma_dev_setup_pSeriesLP()
1531 pci_domain_nr(pci->phb->bus), 0); in pci_dma_dev_setup_pSeriesLP()