Lines Matching refs:insn
85 #define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4) argument
118 #define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) argument
119 #define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3)) argument
120 #define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5) argument
128 #define REG_OFFSET(insn, pos) \ argument
129 (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
131 #define REG_PTR(insn, pos, regs) \ argument
132 (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
134 #define GET_RM(insn) (((insn) >> 12) & 7) argument
136 #define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs)) argument
137 #define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs)) argument
138 #define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs)) argument
139 #define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs)) argument
140 #define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs)) argument
142 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val)) argument
143 #define IMM_I(insn) ((s32)(insn) >> 20) argument
144 #define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \ argument
145 (s32)(((insn) >> 7) & 0x1f))
148 #define GET_PRECISION(insn) (((insn) >> 25) & 3) argument
149 #define GET_RM(insn) (((insn) >> 12) & 7) argument
156 #define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \ argument
160 asm (#insn " %0, %1" \
165 #define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn) \ argument
168 asm volatile (#insn " %0, %1\n" \
227 : [insn] "=&r" (val), [tmp] "=&r" (tmp)
244 unsigned long insn = get_insn(epc); in handle_misaligned_load() local
250 if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) { in handle_misaligned_load()
254 } else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) { in handle_misaligned_load()
257 } else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) { in handle_misaligned_load()
260 } else if ((insn & INSN_MASK_FLD) == INSN_MATCH_FLD) { in handle_misaligned_load()
263 } else if ((insn & INSN_MASK_FLW) == INSN_MATCH_FLW) { in handle_misaligned_load()
266 } else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) { in handle_misaligned_load()
269 } else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) { in handle_misaligned_load()
272 } else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) { in handle_misaligned_load()
275 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
276 } else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP && in handle_misaligned_load()
277 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_load()
281 } else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) { in handle_misaligned_load()
284 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
285 } else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP && in handle_misaligned_load()
286 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_load()
289 } else if ((insn & INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) { in handle_misaligned_load()
292 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
293 } else if ((insn & INSN_MASK_C_FLDSP) == INSN_MATCH_C_FLDSP) { in handle_misaligned_load()
297 } else if ((insn & INSN_MASK_C_FLW) == INSN_MATCH_C_FLW) { in handle_misaligned_load()
300 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
301 } else if ((insn & INSN_MASK_C_FLWSP) == INSN_MATCH_C_FLWSP) { in handle_misaligned_load()
316 SET_RD(insn, regs, val.data_ulong << shift >> shift); in handle_misaligned_load()
318 regs->epc = epc + INSN_LEN(insn); in handle_misaligned_load()
327 unsigned long insn = get_insn(epc); in handle_misaligned_store() local
333 val.data_ulong = GET_RS2(insn, regs); in handle_misaligned_store()
335 if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) { in handle_misaligned_store()
338 } else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) { in handle_misaligned_store()
341 } else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) { in handle_misaligned_store()
344 } else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) { in handle_misaligned_store()
346 val.data_ulong = GET_RS2S(insn, regs); in handle_misaligned_store()
347 } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP && in handle_misaligned_store()
348 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_store()
350 val.data_ulong = GET_RS2C(insn, regs); in handle_misaligned_store()
352 } else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) { in handle_misaligned_store()
354 val.data_ulong = GET_RS2S(insn, regs); in handle_misaligned_store()
355 } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP && in handle_misaligned_store()
356 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_store()
358 val.data_ulong = GET_RS2C(insn, regs); in handle_misaligned_store()
367 regs->epc = epc + INSN_LEN(insn); in handle_misaligned_store()