Lines Matching refs:master
46 static inline bool clk_master_ready(struct clk_master *master) in clk_master_ready() argument
48 unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY; in clk_master_ready()
51 regmap_read(master->regmap, AT91_PMC_SR, &status); in clk_master_ready()
58 struct clk_master *master = to_clk_master(hw); in clk_master_prepare() local
61 spin_lock_irqsave(master->lock, flags); in clk_master_prepare()
63 while (!clk_master_ready(master)) in clk_master_prepare()
66 spin_unlock_irqrestore(master->lock, flags); in clk_master_prepare()
73 struct clk_master *master = to_clk_master(hw); in clk_master_is_prepared() local
77 spin_lock_irqsave(master->lock, flags); in clk_master_is_prepared()
78 status = clk_master_ready(master); in clk_master_is_prepared()
79 spin_unlock_irqrestore(master->lock, flags); in clk_master_is_prepared()
89 struct clk_master *master = to_clk_master(hw); in clk_master_div_recalc_rate() local
90 const struct clk_master_layout *layout = master->layout; in clk_master_div_recalc_rate()
92 master->characteristics; in clk_master_div_recalc_rate()
95 spin_lock_irqsave(master->lock, flags); in clk_master_div_recalc_rate()
96 regmap_read(master->regmap, master->layout->offset, &mckr); in clk_master_div_recalc_rate()
97 spin_unlock_irqrestore(master->lock, flags); in clk_master_div_recalc_rate()
115 struct clk_master *master = to_clk_master(hw); in clk_master_div_save_context() local
120 spin_lock_irqsave(master->lock, flags); in clk_master_div_save_context()
121 regmap_read(master->regmap, master->layout->offset, &mckr); in clk_master_div_save_context()
122 spin_unlock_irqrestore(master->lock, flags); in clk_master_div_save_context()
124 mckr &= master->layout->mask; in clk_master_div_save_context()
126 div = master->characteristics->divisors[div]; in clk_master_div_save_context()
128 master->pms.parent_rate = clk_hw_get_rate(parent_hw); in clk_master_div_save_context()
129 master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div); in clk_master_div_save_context()
136 struct clk_master *master = to_clk_master(hw); in clk_master_div_restore_context() local
141 spin_lock_irqsave(master->lock, flags); in clk_master_div_restore_context()
142 regmap_read(master->regmap, master->layout->offset, &mckr); in clk_master_div_restore_context()
143 spin_unlock_irqrestore(master->lock, flags); in clk_master_div_restore_context()
145 mckr &= master->layout->mask; in clk_master_div_restore_context()
147 div = master->characteristics->divisors[div]; in clk_master_div_restore_context()
149 if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate)) in clk_master_div_restore_context()
162 static int clk_master_div_set(struct clk_master *master, in clk_master_div_set() argument
166 master->characteristics; in clk_master_div_set()
188 ret = regmap_read(master->regmap, master->layout->offset, &mckr); in clk_master_div_set()
192 mckr &= master->layout->mask; in clk_master_div_set()
205 ret = regmap_write(master->regmap, master->layout->offset, mckr); in clk_master_div_set()
209 while (!clk_master_ready(master)) in clk_master_div_set()
212 master->div = characteristics->divisors[div_index]; in clk_master_div_set()
220 struct clk_master *master = to_clk_master(hw); in clk_master_div_recalc_rate_chg() local
222 return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div); in clk_master_div_recalc_rate_chg()
227 struct clk_master *master = to_clk_master(hw); in clk_master_div_restore_context_chg() local
231 spin_lock_irqsave(master->lock, flags); in clk_master_div_restore_context_chg()
232 ret = clk_master_div_set(master, master->pms.parent_rate, in clk_master_div_restore_context_chg()
233 DIV_ROUND_CLOSEST(master->pms.parent_rate, in clk_master_div_restore_context_chg()
234 master->pms.rate)); in clk_master_div_restore_context_chg()
235 spin_unlock_irqrestore(master->lock, flags); in clk_master_div_restore_context_chg()
380 struct clk_master *master = to_clk_master(hw); in clk_master_pres_determine_rate() local
383 master->characteristics; in clk_master_pres_determine_rate()
389 if (master->chg_pid < 0) in clk_master_pres_determine_rate()
392 parent = clk_hw_get_parent_by_index(hw, master->chg_pid); in clk_master_pres_determine_rate()
418 struct clk_master *master = to_clk_master(hw); in clk_master_pres_set_rate() local
432 spin_lock_irqsave(master->lock, flags); in clk_master_pres_set_rate()
433 ret = regmap_read(master->regmap, master->layout->offset, &mckr); in clk_master_pres_set_rate()
437 mckr &= master->layout->mask; in clk_master_pres_set_rate()
438 tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK; in clk_master_pres_set_rate()
442 mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift); in clk_master_pres_set_rate()
443 mckr |= (pres << master->layout->pres_shift); in clk_master_pres_set_rate()
444 ret = regmap_write(master->regmap, master->layout->offset, mckr); in clk_master_pres_set_rate()
448 while (!clk_master_ready(master)) in clk_master_pres_set_rate()
451 spin_unlock_irqrestore(master->lock, flags); in clk_master_pres_set_rate()
459 struct clk_master *master = to_clk_master(hw); in clk_master_pres_recalc_rate() local
461 master->characteristics; in clk_master_pres_recalc_rate()
465 spin_lock_irqsave(master->lock, flags); in clk_master_pres_recalc_rate()
466 regmap_read(master->regmap, master->layout->offset, &val); in clk_master_pres_recalc_rate()
467 spin_unlock_irqrestore(master->lock, flags); in clk_master_pres_recalc_rate()
469 val &= master->layout->mask; in clk_master_pres_recalc_rate()
470 pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; in clk_master_pres_recalc_rate()
481 struct clk_master *master = to_clk_master(hw); in clk_master_pres_get_parent() local
485 spin_lock_irqsave(master->lock, flags); in clk_master_pres_get_parent()
486 regmap_read(master->regmap, master->layout->offset, &mckr); in clk_master_pres_get_parent()
487 spin_unlock_irqrestore(master->lock, flags); in clk_master_pres_get_parent()
489 mckr &= master->layout->mask; in clk_master_pres_get_parent()
496 struct clk_master *master = to_clk_master(hw); in clk_master_pres_save_context() local
501 spin_lock_irqsave(master->lock, flags); in clk_master_pres_save_context()
502 regmap_read(master->regmap, master->layout->offset, &val); in clk_master_pres_save_context()
503 spin_unlock_irqrestore(master->lock, flags); in clk_master_pres_save_context()
505 val &= master->layout->mask; in clk_master_pres_save_context()
506 pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; in clk_master_pres_save_context()
507 if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) in clk_master_pres_save_context()
512 master->pms.parent = val & AT91_PMC_CSS; in clk_master_pres_save_context()
513 master->pms.parent_rate = clk_hw_get_rate(parent_hw); in clk_master_pres_save_context()
514 master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres); in clk_master_pres_save_context()
521 struct clk_master *master = to_clk_master(hw); in clk_master_pres_restore_context() local
525 spin_lock_irqsave(master->lock, flags); in clk_master_pres_restore_context()
526 regmap_read(master->regmap, master->layout->offset, &val); in clk_master_pres_restore_context()
527 spin_unlock_irqrestore(master->lock, flags); in clk_master_pres_restore_context()
529 val &= master->layout->mask; in clk_master_pres_restore_context()
530 pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; in clk_master_pres_restore_context()
531 if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) in clk_master_pres_restore_context()
536 if (master->pms.rate != in clk_master_pres_restore_context()
537 DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) || in clk_master_pres_restore_context()
538 (master->pms.parent != (val & AT91_PMC_CSS))) in clk_master_pres_restore_context()
544 struct clk_master *master = to_clk_master(hw); in clk_master_pres_restore_context_chg() local
546 clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate); in clk_master_pres_restore_context_chg()
578 struct clk_master *master; in at91_clk_register_master_internal() local
588 master = kzalloc(sizeof(*master), GFP_KERNEL); in at91_clk_register_master_internal()
589 if (!master) in at91_clk_register_master_internal()
598 master->hw.init = &init; in at91_clk_register_master_internal()
599 master->layout = layout; in at91_clk_register_master_internal()
600 master->characteristics = characteristics; in at91_clk_register_master_internal()
601 master->regmap = regmap; in at91_clk_register_master_internal()
602 master->chg_pid = chg_pid; in at91_clk_register_master_internal()
603 master->lock = lock; in at91_clk_register_master_internal()
606 spin_lock_irqsave(master->lock, irqflags); in at91_clk_register_master_internal()
607 regmap_read(master->regmap, master->layout->offset, &mckr); in at91_clk_register_master_internal()
608 spin_unlock_irqrestore(master->lock, irqflags); in at91_clk_register_master_internal()
612 master->div = characteristics->divisors[mckr]; in at91_clk_register_master_internal()
615 hw = &master->hw; in at91_clk_register_master_internal()
616 ret = clk_hw_register(NULL, &master->hw); in at91_clk_register_master_internal()
618 kfree(master); in at91_clk_register_master_internal()
680 struct clk_master *master = to_clk_master(hw); in clk_sama7g5_master_recalc_rate() local
682 return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); in clk_sama7g5_master_recalc_rate()
688 struct clk_master *master = to_clk_master(hw); in clk_sama7g5_master_determine_rate() local
718 if (master->chg_pid < 0) in clk_sama7g5_master_determine_rate()
721 parent = clk_hw_get_parent_by_index(hw, master->chg_pid); in clk_sama7g5_master_determine_rate()
757 struct clk_master *master = to_clk_master(hw); in clk_sama7g5_master_get_parent() local
761 spin_lock_irqsave(master->lock, flags); in clk_sama7g5_master_get_parent()
762 index = clk_mux_val_to_index(&master->hw, master->mux_table, 0, in clk_sama7g5_master_get_parent()
763 master->parent); in clk_sama7g5_master_get_parent()
764 spin_unlock_irqrestore(master->lock, flags); in clk_sama7g5_master_get_parent()
771 struct clk_master *master = to_clk_master(hw); in clk_sama7g5_master_set_parent() local
777 spin_lock_irqsave(master->lock, flags); in clk_sama7g5_master_set_parent()
778 master->parent = clk_mux_index_to_val(master->mux_table, 0, index); in clk_sama7g5_master_set_parent()
779 spin_unlock_irqrestore(master->lock, flags); in clk_sama7g5_master_set_parent()
784 static void clk_sama7g5_master_set(struct clk_master *master, in clk_sama7g5_master_set() argument
790 unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT; in clk_sama7g5_master_set()
791 unsigned int div = master->div << MASTER_DIV_SHIFT; in clk_sama7g5_master_set()
793 spin_lock_irqsave(master->lock, flags); in clk_sama7g5_master_set()
795 regmap_write(master->regmap, AT91_PMC_MCR_V2, in clk_sama7g5_master_set()
796 AT91_PMC_MCR_V2_ID(master->id)); in clk_sama7g5_master_set()
797 regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); in clk_sama7g5_master_set()
798 regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, in clk_sama7g5_master_set()
802 AT91_PMC_MCR_V2_ID(master->id)); in clk_sama7g5_master_set()
807 while ((cparent != master->parent) && !clk_master_ready(master)) in clk_sama7g5_master_set()
810 spin_unlock_irqrestore(master->lock, flags); in clk_sama7g5_master_set()
815 struct clk_master *master = to_clk_master(hw); in clk_sama7g5_master_enable() local
817 clk_sama7g5_master_set(master, 1); in clk_sama7g5_master_enable()
824 struct clk_master *master = to_clk_master(hw); in clk_sama7g5_master_disable() local
827 spin_lock_irqsave(master->lock, flags); in clk_sama7g5_master_disable()
829 regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); in clk_sama7g5_master_disable()
830 regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, in clk_sama7g5_master_disable()
834 AT91_PMC_MCR_V2_ID(master->id)); in clk_sama7g5_master_disable()
836 spin_unlock_irqrestore(master->lock, flags); in clk_sama7g5_master_disable()
841 struct clk_master *master = to_clk_master(hw); in clk_sama7g5_master_is_enabled() local
845 spin_lock_irqsave(master->lock, flags); in clk_sama7g5_master_is_enabled()
847 regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); in clk_sama7g5_master_is_enabled()
848 regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); in clk_sama7g5_master_is_enabled()
850 spin_unlock_irqrestore(master->lock, flags); in clk_sama7g5_master_is_enabled()
858 struct clk_master *master = to_clk_master(hw); in clk_sama7g5_master_set_rate() local
870 spin_lock_irqsave(master->lock, flags); in clk_sama7g5_master_set_rate()
871 master->div = div; in clk_sama7g5_master_set_rate()
872 spin_unlock_irqrestore(master->lock, flags); in clk_sama7g5_master_set_rate()
879 struct clk_master *master = to_clk_master(hw); in clk_sama7g5_master_save_context() local
881 master->pms.status = clk_sama7g5_master_is_enabled(hw); in clk_sama7g5_master_save_context()
888 struct clk_master *master = to_clk_master(hw); in clk_sama7g5_master_restore_context() local
890 if (master->pms.status) in clk_sama7g5_master_restore_context()
891 clk_sama7g5_master_set(master, master->pms.status); in clk_sama7g5_master_restore_context()
915 struct clk_master *master; in at91_clk_sama7g5_register_master() local
926 master = kzalloc(sizeof(*master), GFP_KERNEL); in at91_clk_sama7g5_register_master()
927 if (!master) in at91_clk_sama7g5_register_master()
940 master->hw.init = &init; in at91_clk_sama7g5_register_master()
941 master->regmap = regmap; in at91_clk_sama7g5_register_master()
942 master->id = id; in at91_clk_sama7g5_register_master()
943 master->chg_pid = chg_pid; in at91_clk_sama7g5_register_master()
944 master->lock = lock; in at91_clk_sama7g5_register_master()
945 master->mux_table = mux_table; in at91_clk_sama7g5_register_master()
947 spin_lock_irqsave(master->lock, flags); in at91_clk_sama7g5_register_master()
948 regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); in at91_clk_sama7g5_register_master()
949 regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); in at91_clk_sama7g5_register_master()
950 master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; in at91_clk_sama7g5_register_master()
951 master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT; in at91_clk_sama7g5_register_master()
952 spin_unlock_irqrestore(master->lock, flags); in at91_clk_sama7g5_register_master()
954 hw = &master->hw; in at91_clk_sama7g5_register_master()
955 ret = clk_hw_register(NULL, &master->hw); in at91_clk_sama7g5_register_master()
957 kfree(master); in at91_clk_sama7g5_register_master()