Lines Matching refs:name
75 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ argument
76 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
78 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
80 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
83 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ argument
84 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
86 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
87 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
89 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
90 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
92 #define imx_clk_fixed(name, rate) \ argument
93 to_clk(imx_clk_hw_fixed(name, rate))
95 #define imx_clk_fixed_factor(name, parent, mult, div) \ argument
96 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
98 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
99 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
101 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ argument
102 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
104 #define imx_clk_gate(name, parent, reg, shift) \ argument
105 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
107 #define imx_clk_gate_dis(name, parent, reg, shift) \ argument
108 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
110 #define imx_clk_gate2(name, parent, reg, shift) \ argument
111 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
113 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \ argument
114 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
116 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ argument
117 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
119 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ argument
120 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
122 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
123 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
125 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
126 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
128 #define imx_clk_pllv1(type, name, parent, base) \ argument
129 to_clk(imx_clk_hw_pllv1(type, name, parent, base))
131 #define imx_clk_pllv2(name, parent, base) \ argument
132 to_clk(imx_clk_hw_pllv2(name, parent, base))
134 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
135 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
137 #define imx_clk_hw_gate(name, parent, reg, shift) \ argument
138 imx_clk_hw_gate_flags(name, parent, reg, shift, 0)
140 #define imx_clk_hw_gate2(name, parent, reg, shift) \ argument
141 imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)
143 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \ argument
144 imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)
146 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \ argument
147 __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)
149 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \ argument
150 __imx_clk_hw_gate(name, parent, reg, shift, flags, 0)
152 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \ argument
153 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)
155 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \ argument
156 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)
158 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \ argument
159 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
161 #define imx_clk_hw_gate3(name, parent, reg, shift) \ argument
162 imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)
164 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \ argument
165 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
167 #define imx_clk_hw_gate4(name, parent, reg, shift) \ argument
168 imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)
170 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \ argument
171 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
173 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \ argument
174 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
176 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \ argument
177 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)
179 #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
180 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0)
182 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \ argument
183 …__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_…
185 #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
186 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
188 #define imx_clk_hw_divider(name, parent, reg, shift, width) \ argument
189 __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)
191 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \ argument
192 __imx_clk_hw_divider(name, parent, reg, shift, width, \
195 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \ argument
196 __imx_clk_hw_divider(name, parent, reg, shift, width, flags)
198 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \ argument
199 imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk)
201 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
205 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
208 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
211 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
214 struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
234 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
254 struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
257 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
264 const char *name, unsigned long rate);
267 const char *name, unsigned long rate);
270 const char *name);
272 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
275 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
278 struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,
281 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
285 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
289 struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
295 struct clk_hw *imx8ulp_clk_hw_composite(const char *name,
301 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
305 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
316 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) in imx_clk_hw_fixed() argument
318 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); in imx_clk_hw_fixed()
321 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name, in imx_clk_hw_fixed_factor() argument
324 return clk_hw_register_fixed_factor(NULL, name, parent, in imx_clk_hw_fixed_factor()
328 static inline struct clk_hw *__imx_clk_hw_divider(const char *name, in __imx_clk_hw_divider() argument
333 return clk_hw_register_divider(NULL, name, parent, flags, in __imx_clk_hw_divider()
337 static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent, in __imx_clk_hw_gate() argument
342 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, in __imx_clk_hw_gate()
346 static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent, in __imx_clk_hw_gate2() argument
351 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, in __imx_clk_hw_gate2()
355 static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg, in __imx_clk_hw_mux() argument
359 return clk_hw_register_mux(NULL, name, parents, num_parents, in __imx_clk_hw_mux()
364 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
381 struct clk_hw *__imx8m_clk_hw_composite(const char *name,
388 #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \ argument
389 __imx8m_clk_hw_composite(name, parent_names, \
392 #define imx8m_clk_hw_composite(name, parent_names, reg) \ argument
393 _imx8m_clk_hw_composite(name, parent_names, reg, \
396 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \ argument
397 _imx8m_clk_hw_composite(name, parent_names, reg, \
400 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \ argument
401 _imx8m_clk_hw_composite(name, parent_names, reg, \
404 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \ argument
405 _imx8m_clk_hw_composite(name, parent_names, reg, \
408 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \ argument
409 _imx8m_clk_hw_composite(name, parent_names, reg, \
412 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \ argument
413 _imx8m_clk_hw_composite(name, parent_names, reg, \
417 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \ argument
418 _imx8m_clk_hw_composite(name, parent_names, reg, \
422 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,