Lines Matching refs:parent_name
75 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ argument
76 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
78 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
80 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
83 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ argument
84 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
86 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
87 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
198 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \ argument
199 imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk)
202 const char *parent_name, void __iomem *base,
211 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
235 const char *parent_name, void __iomem *base, u32 div_mask);
255 const char *parent_name, void __iomem *base);
258 const char *parent_name, unsigned long flags,
275 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
279 const char *parent_name, void __iomem *reg, u8 idx);
281 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
364 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
422 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,