Lines Matching refs:bank
104 const struct aspeed_sgpio_bank *bank, in bank_reg() argument
109 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
111 return gpio->base + bank->rdata_reg; in bank_reg()
113 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
115 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
117 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
119 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
121 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
123 return gpio->base + bank->tolerance_regs; in bank_reg()
136 unsigned int bank; in to_bank() local
138 bank = GPIO_BANK(offset); in to_bank()
140 WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks)); in to_bank()
141 return &aspeed_sgpio_banks[bank]; in to_bank()
171 const struct aspeed_sgpio_bank *bank = to_bank(offset); in aspeed_sgpio_get() local
179 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); in aspeed_sgpio_get()
189 const struct aspeed_sgpio_bank *bank = to_bank(offset); in sgpio_set_value() local
198 addr_r = bank_reg(gpio, bank, reg_rdata); in sgpio_set_value()
199 addr_w = bank_reg(gpio, bank, reg_val); in sgpio_set_value()
253 const struct aspeed_sgpio_bank **bank, in irqd_to_aspeed_sgpio_data() argument
263 *bank = to_bank(*offset); in irqd_to_aspeed_sgpio_data()
269 const struct aspeed_sgpio_bank *bank; in aspeed_sgpio_irq_ack() local
276 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_irq_ack()
278 status_addr = bank_reg(gpio, bank, reg_irq_status); in aspeed_sgpio_irq_ack()
289 const struct aspeed_sgpio_bank *bank; in aspeed_sgpio_irq_set_mask() local
296 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_irq_set_mask()
297 addr = bank_reg(gpio, bank, reg_irq_enable); in aspeed_sgpio_irq_set_mask()
328 const struct aspeed_sgpio_bank *bank; in aspeed_sgpio_set_type() local
335 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_set_type()
360 addr = bank_reg(gpio, bank, reg_irq_type0); in aspeed_sgpio_set_type()
365 addr = bank_reg(gpio, bank, reg_irq_type1); in aspeed_sgpio_set_type()
370 addr = bank_reg(gpio, bank, reg_irq_type2); in aspeed_sgpio_set_type()
393 const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i]; in aspeed_sgpio_irq_handler() local
395 reg = ioread32(bank_reg(data, bank, reg_irq_status)); in aspeed_sgpio_irq_handler()
408 const struct aspeed_sgpio_bank *bank; in aspeed_sgpio_setup_irqs() local
419 bank = &aspeed_sgpio_banks[i]; in aspeed_sgpio_setup_irqs()
421 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable)); in aspeed_sgpio_setup_irqs()
423 iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status)); in aspeed_sgpio_setup_irqs()
444 bank = &aspeed_sgpio_banks[i]; in aspeed_sgpio_setup_irqs()
446 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0)); in aspeed_sgpio_setup_irqs()
448 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1)); in aspeed_sgpio_setup_irqs()
450 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2)); in aspeed_sgpio_setup_irqs()