Lines Matching refs:amdgpu_device
208 int (*ras_late_init)(struct amdgpu_device *adev);
209 void (*ras_fini)(struct amdgpu_device *adev);
210 int (*ras_error_inject)(struct amdgpu_device *adev,
212 int (*query_ras_error_count)(struct amdgpu_device *adev,
214 void (*reset_ras_error_count)(struct amdgpu_device *adev);
215 void (*query_ras_error_status)(struct amdgpu_device *adev);
216 void (*reset_ras_error_status)(struct amdgpu_device *adev);
217 void (*enable_watchdog_timer)(struct amdgpu_device *adev);
222 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
223 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
225 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
227 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
230 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
233 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
235 void (*init_spm_golden)(struct amdgpu_device *adev);
236 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
361 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
362 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
367 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
373 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
374 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
377 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
379 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
380 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
381 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
383 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
384 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
386 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
388 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
390 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
392 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
394 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
396 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
398 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
400 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
401 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
402 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
403 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
404 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
407 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
410 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
411 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
412 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
413 void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);