Lines Matching refs:ih
41 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, in amdgpu_ih_ring_init() argument
50 ih->ring_size = ring_size; in amdgpu_ih_ring_init()
51 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
52 ih->rptr = 0; in amdgpu_ih_ring_init()
53 ih->use_bus_addr = use_bus_addr; in amdgpu_ih_ring_init()
58 if (ih->ring) in amdgpu_ih_ring_init()
64 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8, in amdgpu_ih_ring_init()
66 if (ih->ring == NULL) in amdgpu_ih_ring_init()
69 ih->gpu_addr = dma_addr; in amdgpu_ih_ring_init()
70 ih->wptr_addr = dma_addr + ih->ring_size; in amdgpu_ih_ring_init()
71 ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; in amdgpu_ih_ring_init()
72 ih->rptr_addr = dma_addr + ih->ring_size + 4; in amdgpu_ih_ring_init()
73 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; in amdgpu_ih_ring_init()
87 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE, in amdgpu_ih_ring_init()
89 &ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_init()
90 (void **)&ih->ring); in amdgpu_ih_ring_init()
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
98 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; in amdgpu_ih_ring_init()
99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; in amdgpu_ih_ring_init()
100 ih->rptr_cpu = &adev->wb.wb[rptr_offs]; in amdgpu_ih_ring_init()
103 init_waitqueue_head(&ih->wait_process); in amdgpu_ih_ring_init()
116 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) in amdgpu_ih_ring_fini() argument
119 if (!ih->ring) in amdgpu_ih_ring_fini()
122 if (ih->use_bus_addr) { in amdgpu_ih_ring_fini()
127 dma_free_coherent(adev->dev, ih->ring_size + 8, in amdgpu_ih_ring_fini()
128 (void *)ih->ring, ih->gpu_addr); in amdgpu_ih_ring_fini()
129 ih->ring = NULL; in amdgpu_ih_ring_fini()
131 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_fini()
132 (void **)&ih->ring); in amdgpu_ih_ring_fini()
133 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
134 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
148 void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv, in amdgpu_ih_ring_write() argument
151 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; in amdgpu_ih_ring_write()
155 ih->ring[wptr++] = cpu_to_le32(iv[i]); in amdgpu_ih_ring_write()
158 wptr &= ih->ptr_mask; in amdgpu_ih_ring_write()
161 if (wptr != READ_ONCE(ih->rptr)) { in amdgpu_ih_ring_write()
163 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr)); in amdgpu_ih_ring_write()
169 struct amdgpu_ih_ring *ih, in amdgpu_ih_has_checkpoint_processed() argument
173 uint32_t cur_rptr = ih->rptr | (*prev_rptr & ~ih->ptr_mask); in amdgpu_ih_has_checkpoint_processed()
177 cur_rptr += ih->ptr_mask + 1; in amdgpu_ih_has_checkpoint_processed()
182 (cur_rptr & ih->ptr_mask) == amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_has_checkpoint_processed()
194 struct amdgpu_ih_ring *ih) in amdgpu_ih_wait_on_checkpoint_process() argument
198 if (!ih->enabled || adev->shutdown) in amdgpu_ih_wait_on_checkpoint_process()
201 checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_wait_on_checkpoint_process()
204 rptr = READ_ONCE(ih->rptr); in amdgpu_ih_wait_on_checkpoint_process()
208 checkpoint_wptr += ih->ptr_mask + 1; in amdgpu_ih_wait_on_checkpoint_process()
210 return wait_event_interruptible(ih->wait_process, in amdgpu_ih_wait_on_checkpoint_process()
211 amdgpu_ih_has_checkpoint_processed(adev, ih, in amdgpu_ih_wait_on_checkpoint_process()
224 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) in amdgpu_ih_process() argument
229 if (!ih->enabled || adev->shutdown) in amdgpu_ih_process()
232 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process()
236 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); in amdgpu_ih_process()
241 while (ih->rptr != wptr && --count) { in amdgpu_ih_process()
242 amdgpu_irq_dispatch(adev, ih); in amdgpu_ih_process()
243 ih->rptr &= ih->ptr_mask; in amdgpu_ih_process()
246 amdgpu_ih_set_rptr(adev, ih); in amdgpu_ih_process()
247 wake_up_all(&ih->wait_process); in amdgpu_ih_process()
250 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process()
251 if (wptr != ih->rptr) in amdgpu_ih_process()
269 struct amdgpu_ih_ring *ih, in amdgpu_ih_decode_iv_helper() argument
273 u32 ring_index = ih->rptr >> 2; in amdgpu_ih_decode_iv_helper()
276 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in amdgpu_ih_decode_iv_helper()
277 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in amdgpu_ih_decode_iv_helper()
278 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in amdgpu_ih_decode_iv_helper()
279 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in amdgpu_ih_decode_iv_helper()
280 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); in amdgpu_ih_decode_iv_helper()
281 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); in amdgpu_ih_decode_iv_helper()
282 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); in amdgpu_ih_decode_iv_helper()
283 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); in amdgpu_ih_decode_iv_helper()
300 ih->rptr += 32; in amdgpu_ih_decode_iv_helper()