Lines Matching refs:adev
58 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, in gmc_v10_0_ecc_interrupt_state() argument
67 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, in gmc_v10_0_vm_fault_interrupt_state() argument
74 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); in gmc_v10_0_vm_fault_interrupt_state()
76 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); in gmc_v10_0_vm_fault_interrupt_state()
80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); in gmc_v10_0_vm_fault_interrupt_state()
82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); in gmc_v10_0_vm_fault_interrupt_state()
91 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, in gmc_v10_0_process_interrupt() argument
97 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; in gmc_v10_0_process_interrupt()
109 if (entry->ih != &adev->irq.ih_soft && in gmc_v10_0_process_interrupt()
110 amdgpu_gmc_filter_faults(adev, addr, entry->pasid, in gmc_v10_0_process_interrupt()
117 if (entry->ih == &adev->irq.ih) { in gmc_v10_0_process_interrupt()
118 amdgpu_irq_delegate(adev, entry, 8); in gmc_v10_0_process_interrupt()
125 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) in gmc_v10_0_process_interrupt()
129 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
136 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_process_interrupt()
147 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); in gmc_v10_0_process_interrupt()
149 dev_err(adev->dev, in gmc_v10_0_process_interrupt()
156 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", in gmc_v10_0_process_interrupt()
160 if (!amdgpu_sriov_vf(adev)) in gmc_v10_0_process_interrupt()
161 hub->vmhub_funcs->print_l2_protection_fault_status(adev, in gmc_v10_0_process_interrupt()
177 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) in gmc_v10_0_set_irq_funcs() argument
179 adev->gmc.vm_fault.num_types = 1; in gmc_v10_0_set_irq_funcs()
180 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; in gmc_v10_0_set_irq_funcs()
182 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_set_irq_funcs()
183 adev->gmc.ecc_irq.num_types = 1; in gmc_v10_0_set_irq_funcs()
184 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; in gmc_v10_0_set_irq_funcs()
195 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, in gmc_v10_0_use_invalidate_semaphore() argument
200 (!amdgpu_sriov_vf(adev))); in gmc_v10_0_use_invalidate_semaphore()
204 struct amdgpu_device *adev, in gmc_v10_0_get_atc_vmid_pasid_mapping_info() argument
223 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, in gmc_v10_0_flush_vm_hub() argument
226 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); in gmc_v10_0_flush_vm_hub()
227 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; in gmc_v10_0_flush_vm_hub()
238 spin_lock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_vm_hub()
248 for (i = 0; i < adev->usec_timeout; i++) { in gmc_v10_0_flush_vm_hub()
258 if (i >= adev->usec_timeout) in gmc_v10_0_flush_vm_hub()
271 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_vm_hub()
276 for (i = 0; i < adev->usec_timeout; i++) { in gmc_v10_0_flush_vm_hub()
296 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_vm_hub()
298 if (i < adev->usec_timeout) in gmc_v10_0_flush_vm_hub()
314 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, in gmc_v10_0_flush_gpu_tlb() argument
317 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; in gmc_v10_0_flush_gpu_tlb()
324 adev->hdp.funcs->flush_hdp(adev, NULL); in gmc_v10_0_flush_gpu_tlb()
329 if (adev->gfx.kiq.ring.sched.ready && in gmc_v10_0_flush_gpu_tlb()
330 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v10_0_flush_gpu_tlb()
331 down_read_trylock(&adev->reset_sem)) { in gmc_v10_0_flush_gpu_tlb()
332 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; in gmc_v10_0_flush_gpu_tlb()
338 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, in gmc_v10_0_flush_gpu_tlb()
341 up_read(&adev->reset_sem); in gmc_v10_0_flush_gpu_tlb()
345 mutex_lock(&adev->mman.gtt_window_lock); in gmc_v10_0_flush_gpu_tlb()
348 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); in gmc_v10_0_flush_gpu_tlb()
349 mutex_unlock(&adev->mman.gtt_window_lock); in gmc_v10_0_flush_gpu_tlb()
355 if (!adev->mman.buffer_funcs_enabled || in gmc_v10_0_flush_gpu_tlb()
356 !adev->ib_pool_ready || in gmc_v10_0_flush_gpu_tlb()
357 amdgpu_in_reset(adev) || in gmc_v10_0_flush_gpu_tlb()
359 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); in gmc_v10_0_flush_gpu_tlb()
360 mutex_unlock(&adev->mman.gtt_window_lock); in gmc_v10_0_flush_gpu_tlb()
369 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, in gmc_v10_0_flush_gpu_tlb()
374 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); in gmc_v10_0_flush_gpu_tlb()
378 r = amdgpu_job_submit(job, &adev->mman.entity, in gmc_v10_0_flush_gpu_tlb()
383 mutex_unlock(&adev->mman.gtt_window_lock); in gmc_v10_0_flush_gpu_tlb()
394 mutex_unlock(&adev->mman.gtt_window_lock); in gmc_v10_0_flush_gpu_tlb()
408 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, in gmc_v10_0_flush_gpu_tlb_pasid() argument
417 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; in gmc_v10_0_flush_gpu_tlb_pasid()
418 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gmc_v10_0_flush_gpu_tlb_pasid()
421 spin_lock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
429 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
434 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
435 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); in gmc_v10_0_flush_gpu_tlb_pasid()
437 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); in gmc_v10_0_flush_gpu_tlb_pasid()
446 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, in gmc_v10_0_flush_gpu_tlb_pasid()
450 for (i = 0; i < adev->num_vmhubs; i++) in gmc_v10_0_flush_gpu_tlb_pasid()
451 gmc_v10_0_flush_gpu_tlb(adev, vmid, in gmc_v10_0_flush_gpu_tlb_pasid()
454 gmc_v10_0_flush_gpu_tlb(adev, vmid, in gmc_v10_0_flush_gpu_tlb_pasid()
467 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); in gmc_v10_0_emit_flush_gpu_tlb()
468 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in gmc_v10_0_emit_flush_gpu_tlb()
515 struct amdgpu_device *adev = ring->adev; in gmc_v10_0_emit_pasid_mapping() local
559 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) in gmc_v10_0_map_mtype() argument
577 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, in gmc_v10_0_get_vm_pde() argument
581 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); in gmc_v10_0_get_vm_pde()
584 if (!adev->gmc.translate_further) in gmc_v10_0_get_vm_pde()
600 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, in gmc_v10_0_get_vm_pte() argument
619 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) in gmc_v10_0_get_vbios_fb_size() argument
652 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) in gmc_v10_0_set_gmc_funcs() argument
654 if (adev->gmc.gmc_funcs == NULL) in gmc_v10_0_set_gmc_funcs()
655 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; in gmc_v10_0_set_gmc_funcs()
658 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) in gmc_v10_0_set_umc_funcs() argument
660 switch (adev->ip_versions[UMC_HWIP][0]) { in gmc_v10_0_set_umc_funcs()
662 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; in gmc_v10_0_set_umc_funcs()
663 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; in gmc_v10_0_set_umc_funcs()
664 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; in gmc_v10_0_set_umc_funcs()
665 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; in gmc_v10_0_set_umc_funcs()
666 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; in gmc_v10_0_set_umc_funcs()
667 adev->umc.ras_funcs = &umc_v8_7_ras_funcs; in gmc_v10_0_set_umc_funcs()
675 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) in gmc_v10_0_set_mmhub_funcs() argument
677 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v10_0_set_mmhub_funcs()
680 adev->mmhub.funcs = &mmhub_v2_3_funcs; in gmc_v10_0_set_mmhub_funcs()
683 adev->mmhub.funcs = &mmhub_v2_0_funcs; in gmc_v10_0_set_mmhub_funcs()
688 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) in gmc_v10_0_set_gfxhub_funcs() argument
690 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_set_gfxhub_funcs()
697 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; in gmc_v10_0_set_gfxhub_funcs()
700 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; in gmc_v10_0_set_gfxhub_funcs()
708 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_early_init() local
710 gmc_v10_0_set_mmhub_funcs(adev); in gmc_v10_0_early_init()
711 gmc_v10_0_set_gfxhub_funcs(adev); in gmc_v10_0_early_init()
712 gmc_v10_0_set_gmc_funcs(adev); in gmc_v10_0_early_init()
713 gmc_v10_0_set_irq_funcs(adev); in gmc_v10_0_early_init()
714 gmc_v10_0_set_umc_funcs(adev); in gmc_v10_0_early_init()
716 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v10_0_early_init()
717 adev->gmc.shared_aperture_end = in gmc_v10_0_early_init()
718 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; in gmc_v10_0_early_init()
719 adev->gmc.private_aperture_start = 0x1000000000000000ULL; in gmc_v10_0_early_init()
720 adev->gmc.private_aperture_end = in gmc_v10_0_early_init()
721 adev->gmc.private_aperture_start + (4ULL << 30) - 1; in gmc_v10_0_early_init()
728 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_late_init() local
731 r = amdgpu_gmc_allocate_vm_inv_eng(adev); in gmc_v10_0_late_init()
735 r = amdgpu_gmc_ras_late_init(adev); in gmc_v10_0_late_init()
739 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v10_0_late_init()
742 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, in gmc_v10_0_vram_gtt_location() argument
747 base = adev->gfxhub.funcs->get_fb_location(adev); in gmc_v10_0_vram_gtt_location()
750 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; in gmc_v10_0_vram_gtt_location()
752 amdgpu_gmc_vram_location(adev, &adev->gmc, base); in gmc_v10_0_vram_gtt_location()
753 amdgpu_gmc_gart_location(adev, mc); in gmc_v10_0_vram_gtt_location()
754 amdgpu_gmc_agp_location(adev, mc); in gmc_v10_0_vram_gtt_location()
757 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v10_0_vram_gtt_location()
760 adev->vm_manager.vram_base_offset += in gmc_v10_0_vram_gtt_location()
761 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; in gmc_v10_0_vram_gtt_location()
773 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) in gmc_v10_0_mc_init() argument
778 adev->gmc.mc_vram_size = in gmc_v10_0_mc_init()
779 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; in gmc_v10_0_mc_init()
780 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v10_0_mc_init()
782 if (!(adev->flags & AMD_IS_APU)) { in gmc_v10_0_mc_init()
783 r = amdgpu_device_resize_fb_bar(adev); in gmc_v10_0_mc_init()
787 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v10_0_mc_init()
788 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v10_0_mc_init()
791 if (adev->flags & AMD_IS_APU) { in gmc_v10_0_mc_init()
792 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v10_0_mc_init()
793 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v10_0_mc_init()
798 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v10_0_mc_init()
799 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) in gmc_v10_0_mc_init()
800 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; in gmc_v10_0_mc_init()
804 adev->gmc.gart_size = 512ULL << 20; in gmc_v10_0_mc_init()
806 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v10_0_mc_init()
808 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); in gmc_v10_0_mc_init()
813 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) in gmc_v10_0_gart_init() argument
817 if (adev->gart.bo) { in gmc_v10_0_gart_init()
823 r = amdgpu_gart_init(adev); in gmc_v10_0_gart_init()
827 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v10_0_gart_init()
828 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | in gmc_v10_0_gart_init()
831 return amdgpu_gart_table_vram_alloc(adev); in gmc_v10_0_gart_init()
837 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_sw_init() local
839 adev->gfxhub.funcs->init(adev); in gmc_v10_0_sw_init()
841 adev->mmhub.funcs->init(adev); in gmc_v10_0_sw_init()
843 spin_lock_init(&adev->gmc.invalidate_lock); in gmc_v10_0_sw_init()
845 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { in gmc_v10_0_sw_init()
846 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; in gmc_v10_0_sw_init()
847 adev->gmc.vram_width = 64; in gmc_v10_0_sw_init()
849 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; in gmc_v10_0_sw_init()
850 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ in gmc_v10_0_sw_init()
852 r = amdgpu_atomfirmware_get_vram_info(adev, in gmc_v10_0_sw_init()
854 adev->gmc.vram_width = vram_width; in gmc_v10_0_sw_init()
856 adev->gmc.vram_type = vram_type; in gmc_v10_0_sw_init()
857 adev->gmc.vram_vendor = vram_vendor; in gmc_v10_0_sw_init()
860 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
871 adev->num_vmhubs = 2; in gmc_v10_0_sw_init()
877 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); in gmc_v10_0_sw_init()
884 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, in gmc_v10_0_sw_init()
886 &adev->gmc.vm_fault); in gmc_v10_0_sw_init()
891 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, in gmc_v10_0_sw_init()
893 &adev->gmc.vm_fault); in gmc_v10_0_sw_init()
897 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_sw_init()
899 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, in gmc_v10_0_sw_init()
900 &adev->gmc.ecc_irq); in gmc_v10_0_sw_init()
909 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ in gmc_v10_0_sw_init()
911 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); in gmc_v10_0_sw_init()
917 if (adev->gmc.xgmi.supported) { in gmc_v10_0_sw_init()
918 r = adev->gfxhub.funcs->get_xgmi_info(adev); in gmc_v10_0_sw_init()
923 r = gmc_v10_0_mc_init(adev); in gmc_v10_0_sw_init()
927 amdgpu_gmc_get_vbios_allocations(adev); in gmc_v10_0_sw_init()
928 amdgpu_gmc_get_reserved_allocation(adev); in gmc_v10_0_sw_init()
931 r = amdgpu_bo_init(adev); in gmc_v10_0_sw_init()
935 r = gmc_v10_0_gart_init(adev); in gmc_v10_0_sw_init()
945 adev->vm_manager.first_kfd_vmid = 8; in gmc_v10_0_sw_init()
947 amdgpu_vm_manager_init(adev); in gmc_v10_0_sw_init()
959 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) in gmc_v10_0_gart_fini() argument
961 amdgpu_gart_table_vram_free(adev); in gmc_v10_0_gart_fini()
966 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_sw_fini() local
968 amdgpu_vm_manager_fini(adev); in gmc_v10_0_sw_fini()
969 gmc_v10_0_gart_fini(adev); in gmc_v10_0_sw_fini()
970 amdgpu_gem_force_release(adev); in gmc_v10_0_sw_fini()
971 amdgpu_bo_fini(adev); in gmc_v10_0_sw_fini()
976 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) in gmc_v10_0_init_golden_registers() argument
985 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) in gmc_v10_0_gart_enable() argument
990 if (adev->gart.bo == NULL) { in gmc_v10_0_gart_enable()
991 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); in gmc_v10_0_gart_enable()
995 r = amdgpu_gart_table_vram_pin(adev); in gmc_v10_0_gart_enable()
999 r = adev->gfxhub.funcs->gart_enable(adev); in gmc_v10_0_gart_enable()
1003 r = adev->mmhub.funcs->gart_enable(adev); in gmc_v10_0_gart_enable()
1007 adev->hdp.funcs->init_registers(adev); in gmc_v10_0_gart_enable()
1010 adev->hdp.funcs->flush_hdp(adev, NULL); in gmc_v10_0_gart_enable()
1015 adev->gfxhub.funcs->set_fault_enable_default(adev, value); in gmc_v10_0_gart_enable()
1016 adev->mmhub.funcs->set_fault_enable_default(adev, value); in gmc_v10_0_gart_enable()
1017 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); in gmc_v10_0_gart_enable()
1018 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); in gmc_v10_0_gart_enable()
1021 (unsigned)(adev->gmc.gart_size >> 20), in gmc_v10_0_gart_enable()
1022 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); in gmc_v10_0_gart_enable()
1024 adev->gart.ready = true; in gmc_v10_0_gart_enable()
1032 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_hw_init() local
1035 gmc_v10_0_init_golden_registers(adev); in gmc_v10_0_hw_init()
1041 if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) in gmc_v10_0_hw_init()
1042 adev->gfxhub.funcs->utcl2_harvest(adev); in gmc_v10_0_hw_init()
1044 r = gmc_v10_0_gart_enable(adev); in gmc_v10_0_hw_init()
1048 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v10_0_hw_init()
1049 adev->umc.funcs->init_registers(adev); in gmc_v10_0_hw_init()
1061 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) in gmc_v10_0_gart_disable() argument
1063 adev->gfxhub.funcs->gart_disable(adev); in gmc_v10_0_gart_disable()
1064 adev->mmhub.funcs->gart_disable(adev); in gmc_v10_0_gart_disable()
1065 amdgpu_gart_table_vram_unpin(adev); in gmc_v10_0_gart_disable()
1070 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_hw_fini() local
1072 gmc_v10_0_gart_disable(adev); in gmc_v10_0_hw_fini()
1074 if (amdgpu_sriov_vf(adev)) { in gmc_v10_0_hw_fini()
1080 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); in gmc_v10_0_hw_fini()
1081 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v10_0_hw_fini()
1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_suspend() local
1090 gmc_v10_0_hw_fini(adev); in gmc_v10_0_suspend()
1098 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_resume() local
1100 r = gmc_v10_0_hw_init(adev); in gmc_v10_0_resume()
1104 amdgpu_vmid_reset_all(adev); in gmc_v10_0_resume()
1130 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_set_clockgating_state() local
1132 r = adev->mmhub.funcs->set_clockgating(adev, state); in gmc_v10_0_set_clockgating_state()
1136 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) in gmc_v10_0_set_clockgating_state()
1137 return athub_v2_1_set_clockgating(adev, state); in gmc_v10_0_set_clockgating_state()
1139 return athub_v2_0_set_clockgating(adev, state); in gmc_v10_0_set_clockgating_state()
1144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gmc_v10_0_get_clockgating_state() local
1146 adev->mmhub.funcs->get_clockgating(adev, flags); in gmc_v10_0_get_clockgating_state()
1148 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) in gmc_v10_0_get_clockgating_state()
1149 athub_v2_1_get_clockgating(adev, flags); in gmc_v10_0_get_clockgating_state()
1151 athub_v2_0_get_clockgating(adev, flags); in gmc_v10_0_get_clockgating_state()