Lines Matching refs:adev
156 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc15_query_video_codecs() argument
159 if (adev->ip_versions[VCE_HWIP][0]) { in soc15_query_video_codecs()
160 switch (adev->ip_versions[VCE_HWIP][0]) { in soc15_query_video_codecs()
172 switch (adev->ip_versions[UVD_HWIP][0]) { in soc15_query_video_codecs()
197 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg() argument
200 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
201 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
203 return amdgpu_device_indirect_rreg(adev, address, data, reg); in soc15_pcie_rreg()
206 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_pcie_wreg() argument
210 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
211 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
213 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in soc15_pcie_wreg()
216 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg64() argument
219 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg64()
220 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg64()
222 return amdgpu_device_indirect_rreg64(adev, address, data, reg); in soc15_pcie_rreg64()
225 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) in soc15_pcie_wreg64() argument
229 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg64()
230 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg64()
232 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); in soc15_pcie_wreg64()
235 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in soc15_uvd_ctx_rreg() argument
243 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
246 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
250 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_uvd_ctx_wreg() argument
257 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
260 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
263 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc15_didt_rreg() argument
271 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
274 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
278 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_didt_wreg() argument
285 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
288 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
291 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_gc_cac_rreg() argument
296 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
299 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
303 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_gc_cac_wreg() argument
307 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
310 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
313 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_se_cac_rreg() argument
318 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
321 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
325 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_se_cac_wreg() argument
329 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
332 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
335 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) in soc15_get_config_memsize() argument
337 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
340 static u32 soc15_get_xclk(struct amdgpu_device *adev) in soc15_get_xclk() argument
342 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
344 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) || in soc15_get_xclk()
345 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1)) in soc15_get_xclk()
347 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) || in soc15_get_xclk()
348 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1)) in soc15_get_xclk()
355 void soc15_grbm_select(struct amdgpu_device *adev, in soc15_grbm_select() argument
367 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) in soc15_vga_set_state() argument
372 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) in soc15_read_disabled_bios() argument
378 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, in soc15_read_bios_from_rom() argument
391 if (adev->flags & AMD_IS_APU) in soc15_read_bios_from_rom()
398 adev->smuio.funcs->get_rom_index_offset(adev); in soc15_read_bios_from_rom()
400 adev->smuio.funcs->get_rom_data_offset(adev); in soc15_read_bios_from_rom()
434 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
439 mutex_lock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
441 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
446 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in soc15_read_indexed_register()
447 mutex_unlock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
451 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, in soc15_get_register_value() argument
456 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
459 return adev->gfx.config.gb_addr_config; in soc15_get_register_value()
461 return adev->gfx.config.db_debug2; in soc15_get_register_value()
466 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
475 if (adev->reg_offset[en->hwip][en->inst] && in soc15_read_register()
476 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
480 *value = soc15_get_register_value(adev, in soc15_read_register()
500 void soc15_program_register_sequence(struct amdgpu_device *adev, in soc15_program_register_sequence() argument
510 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
535 static int soc15_asic_baco_reset(struct amdgpu_device *adev) in soc15_asic_baco_reset() argument
537 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_baco_reset()
541 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
542 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
544 ret = amdgpu_dpm_baco_reset(adev); in soc15_asic_baco_reset()
549 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
550 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in soc15_asic_baco_reset()
556 soc15_asic_reset_method(struct amdgpu_device *adev) in soc15_asic_reset_method() argument
560 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method()
562 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) in soc15_asic_reset_method()
576 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in soc15_asic_reset_method()
579 switch (adev->ip_versions[MP1_HWIP][0]) { in soc15_asic_reset_method()
587 if (adev->asic_type == CHIP_VEGA20) { in soc15_asic_reset_method()
588 if (adev->psp.sos.fw_version >= 0x80067) in soc15_asic_reset_method()
589 baco_reset = amdgpu_dpm_is_baco_supported(adev); in soc15_asic_reset_method()
594 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
595 adev->pm.fw_version <= 0x283400) in soc15_asic_reset_method()
598 baco_reset = amdgpu_dpm_is_baco_supported(adev); in soc15_asic_reset_method()
619 static int soc15_asic_reset(struct amdgpu_device *adev) in soc15_asic_reset() argument
622 if ((adev->apu_flags & AMD_APU_IS_RAVEN) && in soc15_asic_reset()
623 !(adev->apu_flags & AMD_APU_IS_RAVEN2)) in soc15_asic_reset()
626 switch (soc15_asic_reset_method(adev)) { in soc15_asic_reset()
628 dev_info(adev->dev, "PCI reset\n"); in soc15_asic_reset()
629 return amdgpu_device_pci_reset(adev); in soc15_asic_reset()
631 dev_info(adev->dev, "BACO reset\n"); in soc15_asic_reset()
632 return soc15_asic_baco_reset(adev); in soc15_asic_reset()
634 dev_info(adev->dev, "MODE2 reset\n"); in soc15_asic_reset()
635 return amdgpu_dpm_mode2_reset(adev); in soc15_asic_reset()
637 dev_info(adev->dev, "MODE1 reset\n"); in soc15_asic_reset()
638 return amdgpu_device_mode1_reset(adev); in soc15_asic_reset()
642 static bool soc15_supports_baco(struct amdgpu_device *adev) in soc15_supports_baco() argument
644 switch (adev->ip_versions[MP1_HWIP][0]) { in soc15_supports_baco()
647 if (adev->asic_type == CHIP_VEGA20) { in soc15_supports_baco()
648 if (adev->psp.sos.fw_version >= 0x80067) in soc15_supports_baco()
649 return amdgpu_dpm_is_baco_supported(adev); in soc15_supports_baco()
652 return amdgpu_dpm_is_baco_supported(adev); in soc15_supports_baco()
666 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc15_set_uvd_clocks() argument
679 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
686 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) in soc15_pcie_gen3_enable() argument
688 if (pci_is_root_bus(adev->pdev->bus)) in soc15_pcie_gen3_enable()
694 if (adev->flags & AMD_IS_APU) in soc15_pcie_gen3_enable()
697 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in soc15_pcie_gen3_enable()
704 static void soc15_program_aspm(struct amdgpu_device *adev) in soc15_program_aspm() argument
709 if (!(adev->flags & AMD_IS_APU) && in soc15_program_aspm()
710 (adev->nbio.funcs->program_aspm)) in soc15_program_aspm()
711 adev->nbio.funcs->program_aspm(adev); in soc15_program_aspm()
714 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, in soc15_enable_doorbell_aperture() argument
717 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); in soc15_enable_doorbell_aperture()
718 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); in soc15_enable_doorbell_aperture()
730 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) in soc15_get_rev_id() argument
732 return adev->nbio.funcs->get_rev_id(adev); in soc15_get_rev_id()
735 static void soc15_reg_base_init(struct amdgpu_device *adev) in soc15_reg_base_init() argument
740 switch (adev->asic_type) { in soc15_reg_base_init()
744 vega10_reg_base_init(adev); in soc15_reg_base_init()
750 r = amdgpu_discovery_reg_base_init(adev); in soc15_reg_base_init()
756 vega10_reg_base_init(adev); in soc15_reg_base_init()
759 vega20_reg_base_init(adev); in soc15_reg_base_init()
762 arct_reg_base_init(adev); in soc15_reg_base_init()
765 aldebaran_reg_base_init(adev); in soc15_reg_base_init()
768 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); in soc15_reg_base_init()
773 void soc15_set_virt_ops(struct amdgpu_device *adev) in soc15_set_virt_ops() argument
775 adev->virt.ops = &xgpu_ai_virt_ops; in soc15_set_virt_ops()
780 soc15_reg_base_init(adev); in soc15_set_virt_ops()
783 static bool soc15_need_full_reset(struct amdgpu_device *adev) in soc15_need_full_reset() argument
789 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in soc15_get_pcie_usage() argument
799 if (adev->flags & AMD_IS_APU) in soc15_get_pcie_usage()
836 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in vega20_get_pcie_usage() argument
846 if (adev->flags & AMD_IS_APU) in vega20_get_pcie_usage()
885 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) in soc15_need_reset_on_init() argument
892 if (!amdgpu_passthrough(adev)) in soc15_need_reset_on_init()
895 if (adev->flags & AMD_IS_APU) in soc15_need_reset_on_init()
908 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) in soc15_get_pcie_replay_count() argument
920 static void soc15_pre_asic_init(struct amdgpu_device *adev) in soc15_pre_asic_init() argument
922 gmc_v9_0_restore_registers(adev); in soc15_pre_asic_init()
972 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_early_init() local
974 if (!amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
975 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in soc15_common_early_init()
976 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in soc15_common_early_init()
978 adev->smc_rreg = NULL; in soc15_common_early_init()
979 adev->smc_wreg = NULL; in soc15_common_early_init()
980 adev->pcie_rreg = &soc15_pcie_rreg; in soc15_common_early_init()
981 adev->pcie_wreg = &soc15_pcie_wreg; in soc15_common_early_init()
982 adev->pcie_rreg64 = &soc15_pcie_rreg64; in soc15_common_early_init()
983 adev->pcie_wreg64 = &soc15_pcie_wreg64; in soc15_common_early_init()
984 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; in soc15_common_early_init()
985 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; in soc15_common_early_init()
986 adev->didt_rreg = &soc15_didt_rreg; in soc15_common_early_init()
987 adev->didt_wreg = &soc15_didt_wreg; in soc15_common_early_init()
988 adev->gc_cac_rreg = &soc15_gc_cac_rreg; in soc15_common_early_init()
989 adev->gc_cac_wreg = &soc15_gc_cac_wreg; in soc15_common_early_init()
990 adev->se_cac_rreg = &soc15_se_cac_rreg; in soc15_common_early_init()
991 adev->se_cac_wreg = &soc15_se_cac_wreg; in soc15_common_early_init()
993 adev->rev_id = soc15_get_rev_id(adev); in soc15_common_early_init()
994 adev->external_rev_id = 0xFF; in soc15_common_early_init()
998 switch (adev->ip_versions[GC_HWIP][0]) { in soc15_common_early_init()
1000 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1001 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1020 adev->pg_flags = 0; in soc15_common_early_init()
1021 adev->external_rev_id = 0x1; in soc15_common_early_init()
1024 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1025 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1043 adev->pg_flags = 0; in soc15_common_early_init()
1044 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
1047 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1048 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1066 adev->pg_flags = 0; in soc15_common_early_init()
1067 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
1071 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1073 if (adev->rev_id >= 0x8) in soc15_common_early_init()
1074 adev->apu_flags |= AMD_APU_IS_RAVEN2; in soc15_common_early_init()
1076 if (adev->apu_flags & AMD_APU_IS_RAVEN2) in soc15_common_early_init()
1077 adev->external_rev_id = adev->rev_id + 0x79; in soc15_common_early_init()
1078 else if (adev->apu_flags & AMD_APU_IS_PICASSO) in soc15_common_early_init()
1079 adev->external_rev_id = adev->rev_id + 0x41; in soc15_common_early_init()
1080 else if (adev->rev_id == 1) in soc15_common_early_init()
1081 adev->external_rev_id = adev->rev_id + 0x20; in soc15_common_early_init()
1083 adev->external_rev_id = adev->rev_id + 0x01; in soc15_common_early_init()
1085 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { in soc15_common_early_init()
1086 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1101 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1102 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { in soc15_common_early_init()
1103 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1117 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1121 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1140 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1144 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1145 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1159 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1160 adev->external_rev_id = adev->rev_id + 0x32; in soc15_common_early_init()
1163 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1165 if (adev->apu_flags & AMD_APU_IS_RENOIR) in soc15_common_early_init()
1166 adev->external_rev_id = adev->rev_id + 0x91; in soc15_common_early_init()
1168 adev->external_rev_id = adev->rev_id + 0xa1; in soc15_common_early_init()
1169 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1188 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1194 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1195 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1203 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1204 adev->external_rev_id = adev->rev_id + 0x3c; in soc15_common_early_init()
1211 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1212 amdgpu_virt_init_setting(adev); in soc15_common_early_init()
1213 xgpu_ai_mailbox_set_irq_funcs(adev); in soc15_common_early_init()
1221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_late_init() local
1224 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
1225 xgpu_ai_mailbox_get_irq(adev); in soc15_common_late_init()
1227 if (adev->nbio.ras_funcs && in soc15_common_late_init()
1228 adev->nbio.ras_funcs->ras_late_init) in soc15_common_late_init()
1229 r = adev->nbio.ras_funcs->ras_late_init(adev); in soc15_common_late_init()
1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_sw_init() local
1238 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
1239 xgpu_ai_mailbox_add_irq_id(adev); in soc15_common_sw_init()
1241 adev->df.funcs->sw_init(adev); in soc15_common_sw_init()
1248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_sw_fini() local
1250 if (adev->nbio.ras_funcs && in soc15_common_sw_fini()
1251 adev->nbio.ras_funcs->ras_fini) in soc15_common_sw_fini()
1252 adev->nbio.ras_funcs->ras_fini(adev); in soc15_common_sw_fini()
1253 adev->df.funcs->sw_fini(adev); in soc15_common_sw_fini()
1257 static void soc15_doorbell_range_init(struct amdgpu_device *adev) in soc15_doorbell_range_init() argument
1263 if (!amdgpu_sriov_vf(adev)) { in soc15_doorbell_range_init()
1264 for (i = 0; i < adev->sdma.num_instances; i++) { in soc15_doorbell_range_init()
1265 ring = &adev->sdma.instance[i].ring; in soc15_doorbell_range_init()
1266 adev->nbio.funcs->sdma_doorbell_range(adev, i, in soc15_doorbell_range_init()
1268 adev->doorbell_index.sdma_doorbell_range); in soc15_doorbell_range_init()
1271 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in soc15_doorbell_range_init()
1272 adev->irq.ih.doorbell_index); in soc15_doorbell_range_init()
1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_init() local
1281 soc15_pcie_gen3_enable(adev); in soc15_common_hw_init()
1283 soc15_program_aspm(adev); in soc15_common_hw_init()
1285 adev->nbio.funcs->init_registers(adev); in soc15_common_hw_init()
1290 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
1291 adev->nbio.funcs->remap_hdp_registers(adev); in soc15_common_hw_init()
1294 soc15_enable_doorbell_aperture(adev, true); in soc15_common_hw_init()
1300 soc15_doorbell_range_init(adev); in soc15_common_hw_init()
1307 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_fini() local
1310 soc15_enable_doorbell_aperture(adev, false); in soc15_common_hw_fini()
1311 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
1312 xgpu_ai_mailbox_put_irq(adev); in soc15_common_hw_fini()
1314 if (adev->nbio.ras_if && in soc15_common_hw_fini()
1315 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { in soc15_common_hw_fini()
1316 if (adev->nbio.ras_funcs && in soc15_common_hw_fini()
1317 adev->nbio.ras_funcs->init_ras_controller_interrupt) in soc15_common_hw_fini()
1318 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); in soc15_common_hw_fini()
1319 if (adev->nbio.ras_funcs && in soc15_common_hw_fini()
1320 adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
1321 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc15_common_hw_fini()
1329 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_suspend() local
1331 return soc15_common_hw_fini(adev); in soc15_common_suspend()
1336 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_resume() local
1338 return soc15_common_hw_init(adev); in soc15_common_resume()
1356 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) in soc15_update_drm_clock_gating() argument
1362 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) in soc15_update_drm_clock_gating()
1385 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) in soc15_update_drm_light_sleep() argument
1391 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in soc15_update_drm_light_sleep()
1403 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_set_clockgating_state() local
1405 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
1408 switch (adev->ip_versions[NBIO_HWIP][0]) { in soc15_common_set_clockgating_state()
1412 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1414 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1416 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1418 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1420 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1422 adev->smuio.funcs->update_rom_clock_gating(adev, in soc15_common_set_clockgating_state()
1424 adev->df.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1430 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1432 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1434 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1436 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1438 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1443 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1454 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_get_clockgating_state() local
1457 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
1460 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()
1462 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1464 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) { in soc15_common_get_clockgating_state()
1478 adev->smuio.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1480 adev->df.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()