Lines Matching refs:WREG32
90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_ring_set_wptr()
292 WREG32(mmUVD_CGC_GATE, 0); in uvd_v4_2_start()
299 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v4_2_start()
309 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v4_2_start()
310 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); in uvd_v4_2_start()
312 WREG32(mmUVD_LMI_CTRL, 0x203108); in uvd_v4_2_start()
315 WREG32(mmUVD_MPC_CNTL, tmp | 0x10); in uvd_v4_2_start()
317 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v4_2_start()
318 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v4_2_start()
319 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v4_2_start()
320 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); in uvd_v4_2_start()
321 WREG32(mmUVD_MPC_SET_ALU, 0); in uvd_v4_2_start()
322 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v4_2_start()
372 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v4_2_start()
375 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v4_2_start()
378 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | in uvd_v4_2_start()
382 WREG32(mmUVD_RBC_RB_RPTR, 0x0); in uvd_v4_2_start()
385 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_start()
388 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); in uvd_v4_2_start()
410 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v4_2_stop()
453 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v4_2_stop()
457 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
508 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v4_2_ring_test_ring()
577 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); in uvd_v4_2_mc_resume()
578 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v4_2_mc_resume()
582 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); in uvd_v4_2_mc_resume()
583 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v4_2_mc_resume()
588 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); in uvd_v4_2_mc_resume()
589 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v4_2_mc_resume()
593 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v4_2_mc_resume()
597 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v4_2_mc_resume()
599 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
600 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
601 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
617 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
626 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
653 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v4_2_set_dcm()
730 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | in uvd_v4_2_set_powergating_state()
741 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | in uvd_v4_2_set_powergating_state()