Lines Matching refs:vcn
73 adev->vcn.num_enc_rings = 1; in vcn_v2_0_early_init()
75 adev->vcn.num_enc_rings = 2; in vcn_v2_0_early_init()
101 &adev->vcn.inst->irq); in vcn_v2_0_sw_init()
106 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_sw_init()
109 &adev->vcn.inst->irq); in vcn_v2_0_sw_init()
124 ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_sw_init()
127 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; in vcn_v2_0_sw_init()
130 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, in vcn_v2_0_sw_init()
135 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
136 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
137 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
138 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
139 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
140 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
142 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
143 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); in vcn_v2_0_sw_init()
144 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
145 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_0_sw_init()
146 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
147 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_0_sw_init()
148 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
149 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_0_sw_init()
150 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
151 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); in vcn_v2_0_sw_init()
153 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_sw_init()
156 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_sw_init()
159 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; in vcn_v2_0_sw_init()
161 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i; in vcn_v2_0_sw_init()
163 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, in vcn_v2_0_sw_init()
169 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode; in vcn_v2_0_sw_init()
175 fw_shared = adev->vcn.inst->fw_shared_cpu_addr; in vcn_v2_0_sw_init()
191 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; in vcn_v2_0_sw_fini()
219 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_hw_init()
236 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_hw_init()
237 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_hw_init()
262 cancel_delayed_work_sync(&adev->vcn.idle_work); in vcn_v2_0_hw_fini()
265 (adev->vcn.cur_state != AMD_PG_STATE_GATE && in vcn_v2_0_hw_fini()
323 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume()
339 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
341 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
351 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
353 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
359 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
361 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
367 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr)); in vcn_v2_0_mc_resume()
369 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr)); in vcn_v2_0_mc_resume()
379 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume_dpg_mode()
405 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
408 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
426 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
429 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
446 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
449 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
458 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
461 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
787 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; in vcn_v2_0_start_dpg_mode()
788 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_start_dpg_mode()
800 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr; in vcn_v2_0_start_dpg_mode()
874 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr, in vcn_v2_0_start_dpg_mode()
875 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr - in vcn_v2_0_start_dpg_mode()
876 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr)); in vcn_v2_0_start_dpg_mode()
924 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; in vcn_v2_0_start()
925 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_start()
934 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram); in vcn_v2_0_start()
1075 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v2_0_start()
1084 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v2_0_start()
1199 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1201 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1210 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; in vcn_v2_0_pause_dpg_mode()
1226 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v2_0_pause_dpg_mode()
1236 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v2_0_pause_dpg_mode()
1262 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()
1372 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1374 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1389 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1409 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1430 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1433 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence()
1436 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence()
1439 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence()
1442 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence()
1445 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence()
1448 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence()
1471 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); in vcn_v2_0_dec_ring_emit_ib()
1474 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); in vcn_v2_0_dec_ring_emit_ib()
1476 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); in vcn_v2_0_dec_ring_emit_ib()
1478 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); in vcn_v2_0_dec_ring_emit_ib()
1487 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1490 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1493 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1521 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1524 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1527 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1543 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v2_0_enc_ring_get_rptr()
1560 if (ring == &adev->vcn.inst->ring_enc[0]) { in vcn_v2_0_enc_ring_get_wptr()
1584 if (ring == &adev->vcn.inst->ring_enc[0]) { in vcn_v2_0_enc_ring_set_wptr()
1697 amdgpu_fence_process(&adev->vcn.inst->ring_dec); in vcn_v2_0_process_interrupt()
1700 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); in vcn_v2_0_process_interrupt()
1703 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); in vcn_v2_0_process_interrupt()
1724 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); in vcn_v2_0_dec_ring_test_ring()
1728 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_test_ring()
1730 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); in vcn_v2_0_dec_ring_test_ring()
1734 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); in vcn_v2_0_dec_ring_test_ring()
1761 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; in vcn_v2_0_set_powergating_state()
1765 if (state == adev->vcn.cur_state) in vcn_v2_0_set_powergating_state()
1774 adev->vcn.cur_state = state; in vcn_v2_0_set_powergating_state()
1809 adev->vcn.inst->ring_dec.wptr = 0; in vcn_v2_0_start_mmsch()
1810 adev->vcn.inst->ring_dec.wptr_old = 0; in vcn_v2_0_start_mmsch()
1811 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec); in vcn_v2_0_start_mmsch()
1813 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_start_mmsch()
1814 adev->vcn.inst->ring_enc[i].wptr = 0; in vcn_v2_0_start_mmsch()
1815 adev->vcn.inst->ring_enc[i].wptr_old = 0; in vcn_v2_0_start_mmsch()
1816 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]); in vcn_v2_0_start_mmsch()
1871 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_start_sriov()
1892 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_start_sriov()
1896 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_start_sriov()
1910 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_start_sriov()
1914 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_start_sriov()
1925 lower_32_bits(adev->vcn.inst->gpu_addr + offset + in vcn_v2_0_start_sriov()
1930 upper_32_bits(adev->vcn.inst->gpu_addr + offset + in vcn_v2_0_start_sriov()
1939 for (r = 0; r < adev->vcn.num_enc_rings; ++r) { in vcn_v2_0_start_sriov()
1940 ring = &adev->vcn.inst->ring_enc[r]; in vcn_v2_0_start_sriov()
1953 ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_start_sriov()
2065 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; in vcn_v2_0_set_dec_ring_funcs()
2073 for (i = 0; i < adev->vcn.num_enc_rings; ++i) in vcn_v2_0_set_enc_ring_funcs()
2074 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; in vcn_v2_0_set_enc_ring_funcs()
2086 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1; in vcn_v2_0_set_irq_funcs()
2087 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; in vcn_v2_0_set_irq_funcs()