Lines Matching refs:VCN
88 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); in vcn_v2_5_early_init()
161 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); in vcn_v2_5_sw_init()
163 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init()
165 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
167 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init()
169 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); in vcn_v2_5_sw_init()
324 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
391 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
393 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
395 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
398 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
400 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
403 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_5_mc_resume()
406 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_5_mc_resume()
409 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
411 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
413 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_5_mc_resume()
414 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_5_mc_resume()
417 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
419 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
421 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v2_5_mc_resume()
422 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_mc_resume()
425 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
427 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
429 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
430 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, in vcn_v2_5_mc_resume()
444 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
447 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
450 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
453 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
455 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
457 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
462 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
465 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
469 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_mc_resume_dpg_mode()
475 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
478 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
483 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
486 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
489 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
492 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
494 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
496 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
499 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
503 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
506 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
509 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
511 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
515 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
518 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
521 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
523 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v2_5_mc_resume_dpg_mode()
528 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
547 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
554 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
556 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
578 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
580 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
582 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
603 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
606 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
631 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
633 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
644 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
681 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
685 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
689 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
693 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
712 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
719 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
721 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
741 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
743 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
754 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
765 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v2_5_start_dpg_mode()
768 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v2_5_start_dpg_mode()
771 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v2_5_start_dpg_mode()
784 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
788 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
800 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
803 VCN, 0, mmUVD_MPC_CNTL), in vcn_v2_5_start_dpg_mode()
807 VCN, 0, mmUVD_MPC_SET_MUXA0), in vcn_v2_5_start_dpg_mode()
814 VCN, 0, mmUVD_MPC_SET_MUXB0), in vcn_v2_5_start_dpg_mode()
821 VCN, 0, mmUVD_MPC_SET_MUX), in vcn_v2_5_start_dpg_mode()
829 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); in vcn_v2_5_start_dpg_mode()
831 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); in vcn_v2_5_start_dpg_mode()
835 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
839 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
844 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
848 VCN, 0, mmUVD_MASTINT_EN), in vcn_v2_5_start_dpg_mode()
864 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start_dpg_mode()
867 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
873 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v2_5_start_dpg_mode()
876 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v2_5_start_dpg_mode()
880 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v2_5_start_dpg_mode()
882 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v2_5_start_dpg_mode()
886 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start_dpg_mode()
888 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()
890 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start_dpg_mode()
891 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start_dpg_mode()
896 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
920 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
924 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_5_start()
925 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v2_5_start()
938 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
942 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
946 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); in vcn_v2_5_start()
948 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| in vcn_v2_5_start()
955 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v2_5_start()
958 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); in vcn_v2_5_start()
961 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, in vcn_v2_5_start()
968 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, in vcn_v2_5_start()
975 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, in vcn_v2_5_start()
988 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, in vcn_v2_5_start()
990 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, in vcn_v2_5_start()
994 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
998 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, in vcn_v2_5_start()
1001 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1008 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v2_5_start()
1021 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1025 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1038 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v2_5_start()
1043 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v2_5_start()
1046 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); in vcn_v2_5_start()
1056 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start()
1060 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v2_5_start()
1062 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v2_5_start()
1066 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start()
1068 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start()
1069 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start()
1075 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1076 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1077 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_start()
1078 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1079 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_start()
1084 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1085 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1086 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_start()
1087 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1088 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_start()
1109 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); in vcn_v2_5_mmsch_start()
1110 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); in vcn_v2_5_mmsch_start()
1113 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); in vcn_v2_5_mmsch_start()
1117 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data); in vcn_v2_5_mmsch_start()
1120 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); in vcn_v2_5_mmsch_start()
1123 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_5_mmsch_start()
1129 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); in vcn_v2_5_mmsch_start()
1131 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1135 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1178 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), in vcn_v2_5_sriov_start()
1185 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1189 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1194 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); in vcn_v2_5_sriov_start()
1197 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1201 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1206 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_sriov_start()
1211 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), in vcn_v2_5_sriov_start()
1214 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1218 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1222 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1), in vcn_v2_5_sriov_start()
1225 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1), in vcn_v2_5_sriov_start()
1228 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1233 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1238 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2), in vcn_v2_5_sriov_start()
1241 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2), in vcn_v2_5_sriov_start()
1248 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), in vcn_v2_5_sriov_start()
1251 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), in vcn_v2_5_sriov_start()
1254 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), in vcn_v2_5_sriov_start()
1260 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1264 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1276 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); in vcn_v2_5_sriov_start()
1296 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1300 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); in vcn_v2_5_stop_dpg_mode()
1301 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1303 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); in vcn_v2_5_stop_dpg_mode()
1304 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1306 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v2_5_stop_dpg_mode()
1307 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1309 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1313 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, in vcn_v2_5_stop_dpg_mode()
1333 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1341 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1346 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v2_5_stop()
1348 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v2_5_stop()
1352 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1357 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), in vcn_v2_5_stop()
1362 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_stop()
1367 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_stop()
1371 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v2_5_stop()
1376 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), in vcn_v2_5_stop()
1398 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v2_5_pause_dpg_mode()
1402 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
1410 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_5_pause_dpg_mode()
1413 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v2_5_pause_dpg_mode()
1418 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_pause_dpg_mode()
1426 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
1427 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
1428 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
1429 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1430 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1436 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
1437 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
1438 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
1439 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1440 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1444 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_pause_dpg_mode()
1447 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v2_5_pause_dpg_mode()
1452 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_5_pause_dpg_mode()
1453 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
1473 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); in vcn_v2_5_dec_ring_get_rptr()
1490 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v2_5_dec_ring_get_wptr()
1508 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_dec_ring_set_wptr()
1584 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v2_5_enc_ring_get_rptr()
1586 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); in vcn_v2_5_enc_ring_get_rptr()
1604 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); in vcn_v2_5_enc_ring_get_wptr()
1609 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); in vcn_v2_5_enc_ring_get_wptr()
1629 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
1636 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
1743 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle()
1757 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle()