Lines Matching refs:adev
257 static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode, in vi_query_video_codecs() argument
260 switch (adev->asic_type) { in vi_query_video_codecs()
298 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) in vi_pcie_rreg() argument
303 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
307 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
311 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_pcie_wreg() argument
315 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
320 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
323 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) in vi_smc_rreg() argument
328 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_rreg()
331 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_rreg()
335 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_smc_wreg() argument
339 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_wreg()
342 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_wreg()
349 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) in cz_smc_rreg() argument
354 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cz_smc_rreg()
357 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cz_smc_rreg()
361 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cz_smc_wreg() argument
365 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cz_smc_wreg()
368 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cz_smc_wreg()
371 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in vi_uvd_ctx_rreg() argument
376 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_rreg()
379 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_rreg()
383 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_uvd_ctx_wreg() argument
387 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_wreg()
390 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_wreg()
393 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) in vi_didt_rreg() argument
398 spin_lock_irqsave(&adev->didt_idx_lock, flags); in vi_didt_rreg()
401 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in vi_didt_rreg()
405 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_didt_wreg() argument
409 spin_lock_irqsave(&adev->didt_idx_lock, flags); in vi_didt_wreg()
412 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in vi_didt_wreg()
415 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in vi_gc_cac_rreg() argument
420 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_rreg()
423 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_rreg()
427 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_gc_cac_wreg() argument
431 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_wreg()
434 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_wreg()
485 static void vi_init_golden_registers(struct amdgpu_device *adev) in vi_init_golden_registers() argument
488 mutex_lock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
490 if (amdgpu_sriov_vf(adev)) { in vi_init_golden_registers()
491 xgpu_vi_init_golden_registers(adev); in vi_init_golden_registers()
492 mutex_unlock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
496 switch (adev->asic_type) { in vi_init_golden_registers()
498 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
503 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
508 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
513 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
518 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
529 mutex_unlock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
540 static u32 vi_get_xclk(struct amdgpu_device *adev) in vi_get_xclk() argument
542 u32 reference_clock = adev->clock.spll.reference_freq; in vi_get_xclk()
545 if (adev->flags & AMD_IS_APU) in vi_get_xclk()
572 void vi_srbm_select(struct amdgpu_device *adev, in vi_srbm_select() argument
583 static void vi_vga_set_state(struct amdgpu_device *adev, bool state) in vi_vga_set_state() argument
588 static bool vi_read_disabled_bios(struct amdgpu_device *adev) in vi_read_disabled_bios() argument
598 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
607 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
620 r = amdgpu_read_bios(adev); in vi_read_disabled_bios()
624 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
633 static bool vi_read_bios_from_rom(struct amdgpu_device *adev, in vi_read_bios_from_rom() argument
645 if (adev->flags & AMD_IS_APU) in vi_read_bios_from_rom()
651 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_read_bios_from_rom()
659 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_read_bios_from_rom()
743 static uint32_t vi_get_register_value(struct amdgpu_device *adev, in vi_get_register_value() argument
754 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; in vi_get_register_value()
756 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; in vi_get_register_value()
758 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; in vi_get_register_value()
760 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; in vi_get_register_value()
763 mutex_lock(&adev->grbm_idx_mutex); in vi_get_register_value()
765 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
770 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in vi_get_register_value()
771 mutex_unlock(&adev->grbm_idx_mutex); in vi_get_register_value()
778 return adev->gfx.config.gb_addr_config; in vi_get_register_value()
780 return adev->gfx.config.mc_arb_ramcfg; in vi_get_register_value()
814 return adev->gfx.config.tile_mode_array[idx]; in vi_get_register_value()
832 return adev->gfx.config.macrotile_mode_array[idx]; in vi_get_register_value()
839 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, in vi_read_register() argument
851 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
867 static int vi_asic_pci_config_reset(struct amdgpu_device *adev) in vi_asic_pci_config_reset() argument
872 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in vi_asic_pci_config_reset()
875 pci_clear_master(adev->pdev); in vi_asic_pci_config_reset()
877 amdgpu_device_pci_config_reset(adev); in vi_asic_pci_config_reset()
882 for (i = 0; i < adev->usec_timeout; i++) { in vi_asic_pci_config_reset()
885 pci_set_master(adev->pdev); in vi_asic_pci_config_reset()
886 adev->has_hw_reset = true; in vi_asic_pci_config_reset()
893 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in vi_asic_pci_config_reset()
898 static bool vi_asic_supports_baco(struct amdgpu_device *adev) in vi_asic_supports_baco() argument
900 switch (adev->asic_type) { in vi_asic_supports_baco()
907 return amdgpu_dpm_is_baco_supported(adev); in vi_asic_supports_baco()
914 vi_asic_reset_method(struct amdgpu_device *adev) in vi_asic_reset_method() argument
923 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in vi_asic_reset_method()
926 switch (adev->asic_type) { in vi_asic_reset_method()
933 baco_reset = amdgpu_dpm_is_baco_supported(adev); in vi_asic_reset_method()
955 static int vi_asic_reset(struct amdgpu_device *adev) in vi_asic_reset() argument
959 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { in vi_asic_reset()
960 dev_info(adev->dev, "BACO reset\n"); in vi_asic_reset()
961 r = amdgpu_dpm_baco_reset(adev); in vi_asic_reset()
963 dev_info(adev->dev, "PCI CONFIG reset\n"); in vi_asic_reset()
964 r = vi_asic_pci_config_reset(adev); in vi_asic_reset()
970 static u32 vi_get_config_memsize(struct amdgpu_device *adev) in vi_get_config_memsize() argument
975 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, in vi_set_uvd_clock() argument
982 r = amdgpu_atombios_get_clock_dividers(adev, in vi_set_uvd_clock()
990 if (adev->flags & AMD_IS_APU) in vi_set_uvd_clock()
1000 if (adev->flags & AMD_IS_APU) { in vi_set_uvd_clock()
1021 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in vi_set_uvd_clocks() argument
1025 if (adev->flags & AMD_IS_APU) { in vi_set_uvd_clocks()
1026 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS); in vi_set_uvd_clocks()
1030 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS); in vi_set_uvd_clocks()
1034 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); in vi_set_uvd_clocks()
1038 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in vi_set_uvd_clocks()
1046 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in vi_set_vce_clocks() argument
1056 if (adev->flags & AMD_IS_APU) { in vi_set_vce_clocks()
1068 r = amdgpu_atombios_get_clock_dividers(adev, in vi_set_vce_clocks()
1100 static void vi_pcie_gen3_enable(struct amdgpu_device *adev) in vi_pcie_gen3_enable() argument
1102 if (pci_is_root_bus(adev->pdev->bus)) in vi_pcie_gen3_enable()
1108 if (adev->flags & AMD_IS_APU) in vi_pcie_gen3_enable()
1111 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in vi_pcie_gen3_enable()
1118 static void vi_enable_aspm(struct amdgpu_device *adev) in vi_enable_aspm() argument
1133 static void vi_program_aspm(struct amdgpu_device *adev) in vi_program_aspm() argument
1142 if (adev->flags & AMD_IS_APU || in vi_program_aspm()
1143 adev->asic_type < CHIP_POLARIS10) in vi_program_aspm()
1171 pci_read_config_dword(adev->pdev, PCIE_L1_PM_SUB_CNTL, &data1); in vi_program_aspm()
1195 pci_read_config_dword(adev->pdev, LINK_CAP, &data); in vi_program_aspm()
1269 vi_enable_aspm(adev); in vi_program_aspm()
1282 if ((adev->asic_type == CHIP_POLARIS12 && in vi_program_aspm()
1283 !(ASICID_IS_P23(adev->pdev->device, adev->pdev->revision))) || in vi_program_aspm()
1284 ASIC_IS_P22(adev->asic_type, adev->external_rev_id)) { in vi_program_aspm()
1292 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, in vi_enable_doorbell_aperture() argument
1298 if (adev->flags & AMD_IS_APU) in vi_enable_doorbell_aperture()
1314 static uint32_t vi_get_rev_id(struct amdgpu_device *adev) in vi_get_rev_id() argument
1316 if (adev->flags & AMD_IS_APU) in vi_get_rev_id()
1324 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) in vi_flush_hdp() argument
1334 static void vi_invalidate_hdp(struct amdgpu_device *adev, in vi_invalidate_hdp() argument
1345 static bool vi_need_full_reset(struct amdgpu_device *adev) in vi_need_full_reset() argument
1347 switch (adev->asic_type) { in vi_need_full_reset()
1366 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in vi_get_pcie_usage() argument
1376 if (adev->flags & AMD_IS_APU) in vi_get_pcie_usage()
1412 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev) in vi_get_pcie_replay_count() argument
1424 static bool vi_need_reset_on_init(struct amdgpu_device *adev) in vi_need_reset_on_init() argument
1428 if (adev->flags & AMD_IS_APU) in vi_need_reset_on_init()
1441 static void vi_pre_asic_init(struct amdgpu_device *adev) in vi_pre_asic_init() argument
1474 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_early_init() local
1476 if (adev->flags & AMD_IS_APU) { in vi_common_early_init()
1477 adev->smc_rreg = &cz_smc_rreg; in vi_common_early_init()
1478 adev->smc_wreg = &cz_smc_wreg; in vi_common_early_init()
1480 adev->smc_rreg = &vi_smc_rreg; in vi_common_early_init()
1481 adev->smc_wreg = &vi_smc_wreg; in vi_common_early_init()
1483 adev->pcie_rreg = &vi_pcie_rreg; in vi_common_early_init()
1484 adev->pcie_wreg = &vi_pcie_wreg; in vi_common_early_init()
1485 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; in vi_common_early_init()
1486 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; in vi_common_early_init()
1487 adev->didt_rreg = &vi_didt_rreg; in vi_common_early_init()
1488 adev->didt_wreg = &vi_didt_wreg; in vi_common_early_init()
1489 adev->gc_cac_rreg = &vi_gc_cac_rreg; in vi_common_early_init()
1490 adev->gc_cac_wreg = &vi_gc_cac_wreg; in vi_common_early_init()
1492 adev->asic_funcs = &vi_asic_funcs; in vi_common_early_init()
1494 adev->rev_id = vi_get_rev_id(adev); in vi_common_early_init()
1495 adev->external_rev_id = 0xFF; in vi_common_early_init()
1496 switch (adev->asic_type) { in vi_common_early_init()
1498 adev->cg_flags = 0; in vi_common_early_init()
1499 adev->pg_flags = 0; in vi_common_early_init()
1500 adev->external_rev_id = 0x1; in vi_common_early_init()
1503 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1520 adev->pg_flags = 0; in vi_common_early_init()
1521 adev->external_rev_id = adev->rev_id + 0x3c; in vi_common_early_init()
1524 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1537 adev->pg_flags = 0; in vi_common_early_init()
1538 adev->external_rev_id = adev->rev_id + 0x14; in vi_common_early_init()
1541 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1560 adev->pg_flags = 0; in vi_common_early_init()
1561 adev->external_rev_id = adev->rev_id + 0x5A; in vi_common_early_init()
1564 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1583 adev->pg_flags = 0; in vi_common_early_init()
1584 adev->external_rev_id = adev->rev_id + 0x50; in vi_common_early_init()
1587 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1606 adev->pg_flags = 0; in vi_common_early_init()
1607 adev->external_rev_id = adev->rev_id + 0x64; in vi_common_early_init()
1610 adev->cg_flags = 0; in vi_common_early_init()
1630 adev->pg_flags = 0; in vi_common_early_init()
1631 adev->external_rev_id = adev->rev_id + 0x6E; in vi_common_early_init()
1634 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | in vi_common_early_init()
1650 adev->pg_flags = 0; in vi_common_early_init()
1651 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { in vi_common_early_init()
1652 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG | in vi_common_early_init()
1658 adev->external_rev_id = adev->rev_id + 0x1; in vi_common_early_init()
1661 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | in vi_common_early_init()
1675 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in vi_common_early_init()
1681 adev->external_rev_id = adev->rev_id + 0x61; in vi_common_early_init()
1688 if (amdgpu_sriov_vf(adev)) { in vi_common_early_init()
1689 amdgpu_virt_init_setting(adev); in vi_common_early_init()
1690 xgpu_vi_mailbox_set_irq_funcs(adev); in vi_common_early_init()
1698 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_late_init() local
1700 if (amdgpu_sriov_vf(adev)) in vi_common_late_init()
1701 xgpu_vi_mailbox_get_irq(adev); in vi_common_late_init()
1708 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_sw_init() local
1710 if (amdgpu_sriov_vf(adev)) in vi_common_sw_init()
1711 xgpu_vi_mailbox_add_irq_id(adev); in vi_common_sw_init()
1723 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_hw_init() local
1726 vi_init_golden_registers(adev); in vi_common_hw_init()
1728 vi_pcie_gen3_enable(adev); in vi_common_hw_init()
1730 vi_program_aspm(adev); in vi_common_hw_init()
1732 vi_enable_doorbell_aperture(adev, true); in vi_common_hw_init()
1739 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_hw_fini() local
1742 vi_enable_doorbell_aperture(adev, false); in vi_common_hw_fini()
1744 if (amdgpu_sriov_vf(adev)) in vi_common_hw_fini()
1745 xgpu_vi_mailbox_put_irq(adev); in vi_common_hw_fini()
1752 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_suspend() local
1754 return vi_common_hw_fini(adev); in vi_common_suspend()
1759 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_resume() local
1761 return vi_common_hw_init(adev); in vi_common_resume()
1779 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, in vi_update_bif_medium_grain_light_sleep() argument
1786 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) in vi_update_bif_medium_grain_light_sleep()
1799 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, in vi_update_hdp_medium_grain_clock_gating() argument
1806 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) in vi_update_hdp_medium_grain_clock_gating()
1815 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, in vi_update_hdp_light_sleep() argument
1822 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) in vi_update_hdp_light_sleep()
1831 static void vi_update_drm_light_sleep(struct amdgpu_device *adev, in vi_update_drm_light_sleep() argument
1838 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in vi_update_drm_light_sleep()
1848 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, in vi_update_rom_medium_grain_clock_gating() argument
1855 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) in vi_update_rom_medium_grain_clock_gating()
1871 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_set_clockgating_state_by_smu() local
1873 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1874 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { in vi_common_set_clockgating_state_by_smu()
1878 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) { in vi_common_set_clockgating_state_by_smu()
1888 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1891 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1892 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) { in vi_common_set_clockgating_state_by_smu()
1896 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) { in vi_common_set_clockgating_state_by_smu()
1906 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1909 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1910 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { in vi_common_set_clockgating_state_by_smu()
1914 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) { in vi_common_set_clockgating_state_by_smu()
1924 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1928 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) { in vi_common_set_clockgating_state_by_smu()
1938 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1940 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) { in vi_common_set_clockgating_state_by_smu()
1950 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1953 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) { in vi_common_set_clockgating_state_by_smu()
1964 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1967 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) { in vi_common_set_clockgating_state_by_smu()
1978 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_set_clockgating_state() local
1988 if (amdgpu_sriov_vf(adev)) in vi_common_set_clockgating_state()
1991 switch (adev->asic_type) { in vi_common_set_clockgating_state()
1993 vi_update_bif_medium_grain_light_sleep(adev, in vi_common_set_clockgating_state()
1995 vi_update_hdp_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
1997 vi_update_hdp_light_sleep(adev, in vi_common_set_clockgating_state()
1999 vi_update_rom_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
2004 vi_update_bif_medium_grain_light_sleep(adev, in vi_common_set_clockgating_state()
2006 vi_update_hdp_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
2008 vi_update_hdp_light_sleep(adev, in vi_common_set_clockgating_state()
2010 vi_update_drm_light_sleep(adev, in vi_common_set_clockgating_state()
2018 vi_common_set_clockgating_state_by_smu(adev, state); in vi_common_set_clockgating_state()
2034 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_get_clockgating_state() local
2037 if (amdgpu_sriov_vf(adev)) in vi_common_get_clockgating_state()
2088 void vi_set_virt_ops(struct amdgpu_device *adev) in vi_set_virt_ops() argument
2090 adev->virt.ops = &xgpu_vi_virt_ops; in vi_set_virt_ops()
2093 int vi_set_ip_blocks(struct amdgpu_device *adev) in vi_set_ip_blocks() argument
2095 switch (adev->asic_type) { in vi_set_ip_blocks()
2098 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2099 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block); in vi_set_ip_blocks()
2100 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block); in vi_set_ip_blocks()
2101 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2102 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block); in vi_set_ip_blocks()
2103 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2104 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2105 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2108 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2109 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block); in vi_set_ip_blocks()
2110 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
2111 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2112 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2113 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2114 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
2115 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2117 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2118 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2121 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block); in vi_set_ip_blocks()
2122 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
2123 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); in vi_set_ip_blocks()
2124 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); in vi_set_ip_blocks()
2128 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2129 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
2130 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
2131 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2132 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2133 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2134 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
2135 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2137 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2138 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2141 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block); in vi_set_ip_blocks()
2142 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
2143 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block); in vi_set_ip_blocks()
2144 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); in vi_set_ip_blocks()
2151 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2152 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block); in vi_set_ip_blocks()
2153 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
2154 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2155 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); in vi_set_ip_blocks()
2156 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2157 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2158 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2160 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2161 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2164 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); in vi_set_ip_blocks()
2165 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); in vi_set_ip_blocks()
2166 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); in vi_set_ip_blocks()
2169 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2170 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
2171 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); in vi_set_ip_blocks()
2172 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2173 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2174 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2175 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2176 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2178 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2179 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2182 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); in vi_set_ip_blocks()
2183 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); in vi_set_ip_blocks()
2184 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block); in vi_set_ip_blocks()
2186 amdgpu_device_ip_block_add(adev, &acp_ip_block); in vi_set_ip_blocks()
2190 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2191 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
2192 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); in vi_set_ip_blocks()
2193 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block); in vi_set_ip_blocks()
2194 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2195 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2196 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2197 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2199 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2200 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2203 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); in vi_set_ip_blocks()
2204 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block); in vi_set_ip_blocks()
2205 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); in vi_set_ip_blocks()
2207 amdgpu_device_ip_block_add(adev, &acp_ip_block); in vi_set_ip_blocks()
2218 void legacy_doorbell_index_init(struct amdgpu_device *adev) in legacy_doorbell_index_init() argument
2220 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ; in legacy_doorbell_index_init()
2221 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0; in legacy_doorbell_index_init()
2222 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1; in legacy_doorbell_index_init()
2223 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2; in legacy_doorbell_index_init()
2224 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3; in legacy_doorbell_index_init()
2225 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4; in legacy_doorbell_index_init()
2226 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5; in legacy_doorbell_index_init()
2227 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6; in legacy_doorbell_index_init()
2228 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7; in legacy_doorbell_index_init()
2229 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0; in legacy_doorbell_index_init()
2230 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0; in legacy_doorbell_index_init()
2231 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1; in legacy_doorbell_index_init()
2232 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH; in legacy_doorbell_index_init()
2233 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT; in legacy_doorbell_index_init()