Lines Matching refs:pp_handle
916 return pp_funcs->get_sclk((adev)->powerplay.pp_handle, (low)); in amdgpu_dpm_get_sclk()
923 return pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low)); in amdgpu_dpm_get_mclk()
970 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
982 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
998 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_enter() local
1005 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); in amdgpu_dpm_baco_enter()
1013 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_exit() local
1020 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); in amdgpu_dpm_baco_exit()
1033 adev->powerplay.pp_handle, in amdgpu_dpm_set_mp1_state()
1043 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_is_baco_supported() local
1049 if (pp_funcs->get_asic_baco_capability(pp_handle, &baco_cap)) in amdgpu_dpm_is_baco_supported()
1058 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_mode2_reset() local
1063 return pp_funcs->asic_reset_mode_2(pp_handle); in amdgpu_dpm_mode2_reset()
1069 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_reset() local
1076 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); in amdgpu_dpm_baco_reset()
1081 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); in amdgpu_dpm_baco_reset()
1120 adev->powerplay.pp_handle, type, en); in amdgpu_dpm_switch_power_profile()
1132 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, in amdgpu_dpm_set_xgmi_pstate()
1143 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_df_cstate() local
1146 ret = pp_funcs->set_df_cstate(pp_handle, cstate); in amdgpu_dpm_set_df_cstate()
1163 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_enable_mgpu_fan_boost() local
1169 ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); in amdgpu_dpm_enable_mgpu_fan_boost()
1177 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_clockgating_by_smu() local
1183 ret = pp_funcs->set_clockgating_by_smu(pp_handle, in amdgpu_dpm_set_clockgating_by_smu()
1192 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_smu_i2c_bus_access() local
1198 ret = pp_funcs->smu_i2c_bus_access(pp_handle, in amdgpu_dpm_smu_i2c_bus_access()
1232 ret = pp_funcs->read_sensor((adev)->powerplay.pp_handle, in amdgpu_dpm_read_sensor()
1506 adev->powerplay.pp_handle, in amdgpu_pm_compute_clocks()
1543 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in amdgpu_dpm_enable_uvd()
1605 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle); in amdgpu_pm_load_smu_firmware()