Lines Matching refs:dpcd
158 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay()
160 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_clock_recovery_delay()
167 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in drm_dp_link_train_clock_recovery_delay()
192 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_channel_eq_delay()
195 dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_channel_eq_delay()
508 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_type()
511 return drm_dp_is_branch(dpcd) && in drm_dp_downstream_is_type()
512 dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_downstream_is_type()
525 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_tmds()
529 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_is_tmds()
530 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_is_tmds()
612 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_downstream_port_count()
614 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; in drm_dp_downstream_port_count()
616 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) in drm_dp_downstream_port_count()
623 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_extended_dpcd_caps()
635 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_read_extended_dpcd_caps()
646 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { in drm_dp_read_extended_dpcd_caps()
649 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); in drm_dp_read_extended_dpcd_caps()
653 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) in drm_dp_read_extended_dpcd_caps()
656 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_extended_dpcd_caps()
658 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); in drm_dp_read_extended_dpcd_caps()
677 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_dpcd_caps()
681 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_read_dpcd_caps()
684 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) in drm_dp_read_dpcd_caps()
687 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); in drm_dp_read_dpcd_caps()
691 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_dpcd_caps()
711 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_downstream_info()
720 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) in drm_dp_read_downstream_info()
727 len = drm_dp_downstream_port_count(dpcd); in drm_dp_read_downstream_info()
731 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) in drm_dp_read_downstream_info()
754 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_dotclock()
757 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_dotclock()
760 if (dpcd[DP_DPCD_REV] < 0x11) in drm_dp_downstream_max_dotclock()
765 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_dotclock()
783 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_tmds_clock()
787 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_tmds_clock()
790 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_max_tmds_clock()
791 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_max_tmds_clock()
825 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_tmds_clock()
829 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_tmds_clock()
848 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_min_tmds_clock()
852 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_min_tmds_clock()
855 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_min_tmds_clock()
856 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_min_tmds_clock()
891 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_bpc()
895 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_bpc()
898 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_max_bpc()
899 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_max_bpc()
917 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_bpc()
947 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_420_passthrough()
950 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_420_passthrough()
953 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_420_passthrough()
960 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_420_passthrough()
978 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_444_to_420_conversion()
981 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_444_to_420_conversion()
984 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_444_to_420_conversion()
989 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_444_to_420_conversion()
1009 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_rgb_to_ycbcr_conversion()
1013 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1016 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1021 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1043 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_mode()
1049 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_mode()
1052 if (dpcd[DP_DPCD_REV] < 0x11) in drm_dp_downstream_mode()
1109 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_debug()
1114 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_downstream_debug()
1122 bool branch_device = drm_dp_is_branch(dpcd); in drm_dp_downstream_debug()
1170 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); in drm_dp_downstream_debug()
1174 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid); in drm_dp_downstream_debug()
1178 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid); in drm_dp_downstream_debug()
1182 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid); in drm_dp_downstream_debug()
1196 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_subconnector_type()
1200 if (!drm_dp_is_branch(dpcd)) in drm_dp_subconnector_type()
1203 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { in drm_dp_subconnector_type()
1204 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_subconnector_type()
1253 const u8 *dpcd, in drm_dp_set_subconnector_property() argument
1259 subconnector = drm_dp_subconnector_type(dpcd, port_cap); in drm_dp_set_subconnector_property()
1279 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_sink_count_cap()
1284 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && in drm_dp_read_sink_count_cap()
1285 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && in drm_dp_read_sink_count_cap()
2626 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_get_pcon_max_frl_bw()