Lines Matching refs:phy
42 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
47 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
73 enum phy phy) in icl_set_procmon_ref_values() argument
78 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
80 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in icl_set_procmon_ref_values()
83 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); in icl_set_procmon_ref_values()
85 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
86 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
90 enum phy phy, i915_reg_t reg, u32 mask, in check_phy_reg() argument
99 phy_name(phy), in check_phy_reg()
108 enum phy phy) in icl_verify_procmon_ref_values() argument
113 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_verify_procmon_ref_values()
115 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), in icl_verify_procmon_ref_values()
117 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), in icl_verify_procmon_ref_values()
119 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), in icl_verify_procmon_ref_values()
125 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) in has_phy_misc() argument
137 return phy == PHY_A; in has_phy_misc()
141 return phy < PHY_C; in has_phy_misc()
147 enum phy phy) in icl_combo_phy_enabled() argument
150 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phy_enabled()
151 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
153 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
155 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
185 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) in phy_is_master() argument
203 if (phy == PHY_A) in phy_is_master()
206 return phy == PHY_D; in phy_is_master()
208 return phy == PHY_C; in phy_is_master()
214 enum phy phy) in icl_combo_phy_verify_state() argument
219 if (!icl_combo_phy_enabled(dev_priv, phy)) in icl_combo_phy_verify_state()
223 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy), in icl_combo_phy_verify_state()
229 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy), in icl_combo_phy_verify_state()
234 ret &= icl_verify_procmon_ref_values(dev_priv, phy); in icl_combo_phy_verify_state()
236 if (phy_is_master(dev_priv, phy)) { in icl_combo_phy_verify_state()
237 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), in icl_combo_phy_verify_state()
244 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), in icl_combo_phy_verify_state()
250 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), in icl_combo_phy_verify_state()
257 enum phy phy, bool is_dsi, in intel_combo_phy_power_up_lanes() argument
302 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); in intel_combo_phy_power_up_lanes()
305 intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); in intel_combo_phy_power_up_lanes()
310 enum phy phy; in icl_combo_phys_init() local
312 for_each_combo_phy(dev_priv, phy) { in icl_combo_phys_init()
315 if (icl_combo_phy_verify_state(dev_priv, phy)) { in icl_combo_phys_init()
318 phy_name(phy)); in icl_combo_phys_init()
322 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_init()
333 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
334 if (IS_JSL_EHL(dev_priv) && phy == PHY_A) { in icl_combo_phys_init()
342 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
346 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
350 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
352 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
355 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
358 icl_set_procmon_ref_values(dev_priv, phy); in icl_combo_phys_init()
360 if (phy_is_master(dev_priv, phy)) { in icl_combo_phys_init()
361 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); in icl_combo_phys_init()
363 intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); in icl_combo_phys_init()
366 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); in icl_combo_phys_init()
368 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); in icl_combo_phys_init()
370 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); in icl_combo_phys_init()
372 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); in icl_combo_phys_init()
378 enum phy phy; in icl_combo_phys_uninit() local
380 for_each_combo_phy_reverse(dev_priv, phy) { in icl_combo_phys_uninit()
383 if (phy == PHY_A && in icl_combo_phys_uninit()
384 !icl_combo_phy_verify_state(dev_priv, phy)) { in icl_combo_phys_uninit()
393 phy_name(phy)); in icl_combo_phys_uninit()
397 phy_name(phy)); in icl_combo_phys_uninit()
401 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_uninit()
404 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_uninit()
406 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_uninit()
409 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); in icl_combo_phys_uninit()
411 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); in icl_combo_phys_uninit()