Lines Matching refs:pipe_config
1041 const struct intel_crtc_state *pipe_config) in intel_dp_source_supports_fec() argument
1049 if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A) in intel_dp_source_supports_fec()
1056 const struct intel_crtc_state *pipe_config) in intel_dp_supports_fec() argument
1058 return intel_dp_source_supports_fec(intel_dp, pipe_config) && in intel_dp_supports_fec()
1155 struct intel_crtc_state *pipe_config, in intel_dp_adjust_compliance_config() argument
1165 pipe_config->dither_force_disable = bpp == 6 * 3; in intel_dp_adjust_compliance_config()
1194 struct intel_crtc_state *pipe_config, in intel_dp_compute_link_config_wide() argument
1197 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dp_compute_link_config_wide()
1202 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); in intel_dp_compute_link_config_wide()
1220 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide()
1221 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
1222 pipe_config->port_clock = link_rate; in intel_dp_compute_link_config_wide()
1324 struct intel_crtc_state *pipe_config, in intel_dp_dsc_compute_config() argument
1331 &pipe_config->hw.adjusted_mode; in intel_dp_dsc_compute_config()
1335 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && in intel_dp_dsc_compute_config()
1336 intel_dp_supports_fec(intel_dp, pipe_config); in intel_dp_dsc_compute_config()
1338 if (!intel_dp_supports_dsc(intel_dp, pipe_config)) in intel_dp_dsc_compute_config()
1355 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_config()
1356 pipe_config->port_clock = limits->max_rate; in intel_dp_dsc_compute_config()
1357 pipe_config->lane_count = limits->max_lane_count; in intel_dp_dsc_compute_config()
1360 pipe_config->dsc.compressed_bpp = in intel_dp_dsc_compute_config()
1362 pipe_config->pipe_bpp); in intel_dp_dsc_compute_config()
1363 pipe_config->dsc.slice_count = in intel_dp_dsc_compute_config()
1372 pipe_config->port_clock, in intel_dp_dsc_compute_config()
1373 pipe_config->lane_count, in intel_dp_dsc_compute_config()
1376 pipe_config->bigjoiner, in intel_dp_dsc_compute_config()
1382 pipe_config->bigjoiner); in intel_dp_dsc_compute_config()
1388 pipe_config->dsc.compressed_bpp = min_t(u16, in intel_dp_dsc_compute_config()
1390 pipe_config->pipe_bpp); in intel_dp_dsc_compute_config()
1391 pipe_config->dsc.slice_count = dsc_dp_slice_count; in intel_dp_dsc_compute_config()
1401 pipe_config->dsc.compressed_bpp = in intel_dp_dsc_compute_config()
1416 pipe_config->bigjoiner) { in intel_dp_dsc_compute_config()
1417 if (pipe_config->dsc.slice_count < 2) { in intel_dp_dsc_compute_config()
1423 pipe_config->dsc.dsc_split = true; in intel_dp_dsc_compute_config()
1426 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); in intel_dp_dsc_compute_config()
1431 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
1432 pipe_config->dsc.compressed_bpp); in intel_dp_dsc_compute_config()
1436 pipe_config->dsc.compression_enable = true; in intel_dp_dsc_compute_config()
1439 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
1440 pipe_config->dsc.compressed_bpp, in intel_dp_dsc_compute_config()
1441 pipe_config->dsc.slice_count); in intel_dp_dsc_compute_config()
1448 struct intel_crtc_state *pipe_config, in intel_dp_compute_link_config() argument
1453 &pipe_config->hw.adjusted_mode; in intel_dp_compute_link_config()
1471 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); in intel_dp_compute_link_config()
1472 limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config); in intel_dp_compute_link_config()
1487 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); in intel_dp_compute_link_config()
1496 pipe_config->bigjoiner = true; in intel_dp_compute_link_config()
1502 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); in intel_dp_compute_link_config()
1510 pipe_config->bigjoiner)) { in intel_dp_compute_link_config()
1511 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, in intel_dp_compute_link_config()
1517 if (pipe_config->dsc.compression_enable) { in intel_dp_compute_link_config()
1520 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1521 pipe_config->pipe_bpp, in intel_dp_compute_link_config()
1522 pipe_config->dsc.compressed_bpp); in intel_dp_compute_link_config()
1527 pipe_config->dsc.compressed_bpp), in intel_dp_compute_link_config()
1528 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
1529 pipe_config->lane_count)); in intel_dp_compute_link_config()
1532 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1533 pipe_config->pipe_bpp); in intel_dp_compute_link_config()
1538 pipe_config->pipe_bpp), in intel_dp_compute_link_config()
1539 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
1540 pipe_config->lane_count)); in intel_dp_compute_link_config()
1747 struct intel_crtc_state *pipe_config, in intel_dp_compute_config() argument
1751 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dp_compute_config()
1761 pipe_config->has_pch_encoder = true; in intel_dp_compute_config()
1763 pipe_config->output_format = intel_dp_output_format(&intel_connector->base, in intel_dp_compute_config()
1766 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { in intel_dp_compute_config()
1767 ret = intel_panel_fitting(pipe_config, conn_state); in intel_dp_compute_config()
1773 pipe_config->has_audio = false; in intel_dp_compute_config()
1775 pipe_config->has_audio = intel_dp->has_audio; in intel_dp_compute_config()
1777 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; in intel_dp_compute_config()
1784 ret = intel_panel_fitting(pipe_config, conn_state); in intel_dp_compute_config()
1802 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); in intel_dp_compute_config()
1806 pipe_config->limited_color_range = in intel_dp_compute_config()
1807 intel_dp_limited_color_range(pipe_config, conn_state); in intel_dp_compute_config()
1809 if (pipe_config->dsc.compression_enable) in intel_dp_compute_config()
1810 output_bpp = pipe_config->dsc.compressed_bpp; in intel_dp_compute_config()
1812 output_bpp = intel_dp_output_bpp(pipe_config->output_format, in intel_dp_compute_config()
1813 pipe_config->pipe_bpp); in intel_dp_compute_config()
1819 pipe_config->splitter.enable = true; in intel_dp_compute_config()
1820 pipe_config->splitter.link_count = n; in intel_dp_compute_config()
1821 pipe_config->splitter.pixel_overlap = overlap; in intel_dp_compute_config()
1836 pipe_config->lane_count, in intel_dp_compute_config()
1838 pipe_config->port_clock, in intel_dp_compute_config()
1839 &pipe_config->dp_m_n, in intel_dp_compute_config()
1840 constant_n, pipe_config->fec_enable); in intel_dp_compute_config()
1843 if (pipe_config->splitter.enable) in intel_dp_compute_config()
1844 pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count; in intel_dp_compute_config()
1847 g4x_dp_set_clock(encoder, pipe_config); in intel_dp_compute_config()
1849 intel_vrr_compute_config(pipe_config, conn_state); in intel_dp_compute_config()
1850 intel_psr_compute_config(intel_dp, pipe_config, conn_state); in intel_dp_compute_config()
1851 intel_drrs_compute_config(intel_dp, pipe_config, output_bpp, in intel_dp_compute_config()
1853 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); in intel_dp_compute_config()
1854 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); in intel_dp_compute_config()