Lines Matching refs:DPLL
1454 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1455 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1458 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1470 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1475 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1476 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1606 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _vlv_enable_pll()
1607 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1610 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1626 intel_de_write(dev_priv, DPLL(pipe), in vlv_enable_pll()
1759 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _chv_enable_pll()
1762 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
1778 intel_de_write(dev_priv, DPLL(pipe), in chv_enable_pll()
1804 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll()
1863 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_disable_pll()
1864 intel_de_posting_read(dev_priv, DPLL(pipe)); in vlv_disable_pll()
1880 intel_de_write(dev_priv, DPLL(pipe), val); in chv_disable_pll()
1881 intel_de_posting_read(dev_priv, DPLL(pipe)); in chv_disable_pll()
1906 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1907 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_disable_pll()
1933 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in assert_pll()