Lines Matching refs:engine
21 const struct intel_engine_cs *engine, in set_offsets() argument
32 const u32 base = engine->mmio_base; in set_offsets()
50 if (GRAPHICS_VER(engine->i915) >= 11) in set_offsets()
73 if (GRAPHICS_VER(engine->i915) >= 11) in set_offsets()
611 static const u8 *reg_offsets(const struct intel_engine_cs *engine) in reg_offsets() argument
619 GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 && in reg_offsets()
620 !intel_engine_has_relative_mmio(engine)); in reg_offsets()
622 if (engine->class == RENDER_CLASS) { in reg_offsets()
623 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) in reg_offsets()
625 else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) in reg_offsets()
627 else if (GRAPHICS_VER(engine->i915) >= 12) in reg_offsets()
629 else if (GRAPHICS_VER(engine->i915) >= 11) in reg_offsets()
631 else if (GRAPHICS_VER(engine->i915) >= 9) in reg_offsets()
636 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) in reg_offsets()
638 else if (GRAPHICS_VER(engine->i915) >= 12) in reg_offsets()
640 else if (GRAPHICS_VER(engine->i915) >= 9) in reg_offsets()
647 static int lrc_ring_mi_mode(const struct intel_engine_cs *engine) in lrc_ring_mi_mode() argument
649 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) in lrc_ring_mi_mode()
651 else if (GRAPHICS_VER(engine->i915) >= 12) in lrc_ring_mi_mode()
653 else if (GRAPHICS_VER(engine->i915) >= 9) in lrc_ring_mi_mode()
655 else if (engine->class == RENDER_CLASS) in lrc_ring_mi_mode()
661 static int lrc_ring_gpr0(const struct intel_engine_cs *engine) in lrc_ring_gpr0() argument
663 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) in lrc_ring_gpr0()
665 else if (GRAPHICS_VER(engine->i915) >= 12) in lrc_ring_gpr0()
667 else if (GRAPHICS_VER(engine->i915) >= 9) in lrc_ring_gpr0()
669 else if (engine->class == RENDER_CLASS) in lrc_ring_gpr0()
675 static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine) in lrc_ring_wa_bb_per_ctx() argument
677 if (GRAPHICS_VER(engine->i915) >= 12) in lrc_ring_wa_bb_per_ctx()
679 else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS) in lrc_ring_wa_bb_per_ctx()
685 static int lrc_ring_indirect_ptr(const struct intel_engine_cs *engine) in lrc_ring_indirect_ptr() argument
689 x = lrc_ring_wa_bb_per_ctx(engine); in lrc_ring_indirect_ptr()
696 static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine) in lrc_ring_indirect_offset() argument
700 x = lrc_ring_indirect_ptr(engine); in lrc_ring_indirect_offset()
707 static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine) in lrc_ring_cmd_buf_cctl() argument
710 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) in lrc_ring_cmd_buf_cctl()
716 else if (engine->class != RENDER_CLASS) in lrc_ring_cmd_buf_cctl()
718 else if (GRAPHICS_VER(engine->i915) >= 12) in lrc_ring_cmd_buf_cctl()
720 else if (GRAPHICS_VER(engine->i915) >= 11) in lrc_ring_cmd_buf_cctl()
727 lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine) in lrc_ring_indirect_offset_default() argument
729 switch (GRAPHICS_VER(engine->i915)) { in lrc_ring_indirect_offset_default()
731 MISSING_CASE(GRAPHICS_VER(engine->i915)); in lrc_ring_indirect_offset_default()
746 const struct intel_engine_cs *engine, in lrc_setup_indirect_ctx() argument
752 GEM_BUG_ON(lrc_ring_indirect_ptr(engine) == -1); in lrc_setup_indirect_ctx()
753 regs[lrc_ring_indirect_ptr(engine) + 1] = in lrc_setup_indirect_ctx()
756 GEM_BUG_ON(lrc_ring_indirect_offset(engine) == -1); in lrc_setup_indirect_ctx()
757 regs[lrc_ring_indirect_offset(engine) + 1] = in lrc_setup_indirect_ctx()
758 lrc_ring_indirect_offset_default(engine) << 6; in lrc_setup_indirect_ctx()
763 const struct intel_engine_cs *engine, in init_common_regs() argument
772 if (GRAPHICS_VER(engine->i915) < 11) in init_common_regs()
781 const struct intel_engine_cs *engine) in init_wa_bb_regs() argument
783 const struct i915_ctx_workarounds * const wa_ctx = &engine->wa_ctx; in init_wa_bb_regs()
788 GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1); in init_wa_bb_regs()
789 regs[lrc_ring_wa_bb_per_ctx(engine) + 1] = in init_wa_bb_regs()
794 lrc_setup_indirect_ctx(regs, engine, in init_wa_bb_regs()
825 static void __reset_stop_ring(u32 *regs, const struct intel_engine_cs *engine) in __reset_stop_ring() argument
829 x = lrc_ring_mi_mode(engine); in __reset_stop_ring()
838 const struct intel_engine_cs *engine, in __lrc_init_regs() argument
855 set_offsets(regs, reg_offsets(engine), engine, inhibit); in __lrc_init_regs()
857 init_common_regs(regs, ce, engine, inhibit); in __lrc_init_regs()
860 init_wa_bb_regs(regs, engine); in __lrc_init_regs()
862 __reset_stop_ring(regs, engine); in __lrc_init_regs()
866 const struct intel_engine_cs *engine, in lrc_init_regs() argument
869 __lrc_init_regs(ce->lrc_reg_state, ce, engine, inhibit); in lrc_init_regs()
873 const struct intel_engine_cs *engine) in lrc_reset_regs() argument
875 __reset_stop_ring(ce->lrc_reg_state, engine); in lrc_reset_regs()
879 set_redzone(void *vaddr, const struct intel_engine_cs *engine) in set_redzone() argument
884 vaddr += engine->context_size; in set_redzone()
890 check_redzone(const void *vaddr, const struct intel_engine_cs *engine) in check_redzone() argument
895 vaddr += engine->context_size; in check_redzone()
898 drm_err_once(&engine->i915->drm, in check_redzone()
900 engine->name); in check_redzone()
904 struct intel_engine_cs *engine, in lrc_init_state() argument
909 set_redzone(state, engine); in lrc_init_state()
911 if (engine->default_state) { in lrc_init_state()
912 shmem_read(engine->default_state, 0, in lrc_init_state()
913 state, engine->context_size); in lrc_init_state()
925 __lrc_init_regs(state + LRC_STATE_OFFSET, ce, engine, inhibit); in lrc_init_state()
929 __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine) in __lrc_alloc_state() argument
935 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); in __lrc_alloc_state()
940 if (GRAPHICS_VER(engine->i915) == 12) { in __lrc_alloc_state()
945 if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) { in __lrc_alloc_state()
950 obj = i915_gem_object_create_lmem(engine->i915, context_size, in __lrc_alloc_state()
953 obj = i915_gem_object_create_shmem(engine->i915, context_size); in __lrc_alloc_state()
957 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); in __lrc_alloc_state()
967 pinned_timeline(struct intel_context *ce, struct intel_engine_cs *engine) in pinned_timeline() argument
971 return intel_timeline_create_from_engine(engine, page_unmask_bits(tl)); in pinned_timeline()
974 int lrc_alloc(struct intel_context *ce, struct intel_engine_cs *engine) in lrc_alloc() argument
982 vma = __lrc_alloc_state(ce, engine); in lrc_alloc()
986 ring = intel_engine_create_ring(engine, ce->ring_size); in lrc_alloc()
1000 tl = pinned_timeline(ce, engine); in lrc_alloc()
1002 tl = intel_timeline_create(engine->gt); in lrc_alloc()
1030 lrc_init_regs(ce, ce->engine, true); in lrc_reset()
1031 ce->lrc.lrca = lrc_update_regs(ce, ce->engine, ce->ring->tail); in lrc_reset()
1036 struct intel_engine_cs *engine, in lrc_pre_pin() argument
1044 i915_coherent_map_type(ce->engine->i915, in lrc_pre_pin()
1054 struct intel_engine_cs *engine, in lrc_pin() argument
1060 lrc_init_state(ce, engine, vaddr); in lrc_pin()
1062 ce->lrc.lrca = lrc_update_regs(ce, engine, ce->ring->tail); in lrc_pin()
1069 ce->engine); in lrc_unpin()
1128 GEM_BUG_ON(lrc_ring_gpr0(ce->engine) == -1); in gen12_emit_restore_scratch()
1135 (lrc_ring_gpr0(ce->engine) + 1) * sizeof(u32); in gen12_emit_restore_scratch()
1144 GEM_BUG_ON(lrc_ring_cmd_buf_cctl(ce->engine) == -1); in gen12_emit_cmd_buf_wa()
1151 (lrc_ring_cmd_buf_cctl(ce->engine) + 1) * sizeof(u32); in gen12_emit_cmd_buf_wa()
1202 const struct intel_engine_cs *engine, in setup_indirect_ctx_bb() argument
1213 lrc_setup_indirect_ctx(ce->lrc_reg_state, engine, in setup_indirect_ctx_bb()
1270 const struct intel_engine_cs *engine, in lrc_update_regs() argument
1285 if (engine->class == RENDER_CLASS) { in lrc_update_regs()
1287 intel_sseu_make_rpcs(engine->gt, &ce->sseu); in lrc_update_regs()
1289 i915_oa_init_reg_state(ce, engine); in lrc_update_regs()
1296 if (ce->engine->class == RENDER_CLASS) in lrc_update_regs()
1300 GEM_BUG_ON(engine->wa_ctx.indirect_ctx.size); in lrc_update_regs()
1301 setup_indirect_ctx_bb(ce, engine, fn); in lrc_update_regs()
1308 struct intel_engine_cs *engine) in lrc_update_offsets() argument
1310 set_offsets(ce->lrc_reg_state, reg_offsets(engine), engine, false); in lrc_update_offsets()
1314 const struct intel_engine_cs *engine, in lrc_check_regs() argument
1324 engine->name, in lrc_check_regs()
1334 engine->name, in lrc_check_regs()
1341 x = lrc_ring_mi_mode(engine); in lrc_check_regs()
1344 engine->name, regs[x + 1]); in lrc_check_regs()
1370 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) in gen8_emit_flush_coherentl3_wa() argument
1375 *batch++ = intel_gt_scratch_offset(engine->gt, in gen8_emit_flush_coherentl3_wa()
1390 *batch++ = intel_gt_scratch_offset(engine->gt, in gen8_emit_flush_coherentl3_wa()
1412 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) in gen8_init_indirectctx_bb() argument
1418 if (IS_BROADWELL(engine->i915)) in gen8_init_indirectctx_bb()
1419 batch = gen8_emit_flush_coherentl3_wa(engine, batch); in gen8_init_indirectctx_bb()
1464 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) in gen9_init_indirectctx_bb() argument
1492 batch = gen8_emit_flush_coherentl3_wa(engine, batch); in gen9_init_indirectctx_bb()
1505 if (HAS_POOLED_EU(engine->i915)) { in gen9_init_indirectctx_bb()
1538 static int lrc_create_wa_ctx(struct intel_engine_cs *engine) in lrc_create_wa_ctx() argument
1544 obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_SIZE); in lrc_create_wa_ctx()
1548 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); in lrc_create_wa_ctx()
1554 engine->wa_ctx.vma = vma; in lrc_create_wa_ctx()
1562 void lrc_fini_wa_ctx(struct intel_engine_cs *engine) in lrc_fini_wa_ctx() argument
1564 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); in lrc_fini_wa_ctx()
1567 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1569 void lrc_init_wa_ctx(struct intel_engine_cs *engine) in lrc_init_wa_ctx() argument
1571 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; in lrc_init_wa_ctx()
1581 if (engine->class != RENDER_CLASS) in lrc_init_wa_ctx()
1584 switch (GRAPHICS_VER(engine->i915)) { in lrc_init_wa_ctx()
1597 MISSING_CASE(GRAPHICS_VER(engine->i915)); in lrc_init_wa_ctx()
1601 err = lrc_create_wa_ctx(engine); in lrc_init_wa_ctx()
1608 drm_err(&engine->i915->drm, in lrc_init_wa_ctx()
1614 if (!engine->wa_ctx.vma) in lrc_init_wa_ctx()
1645 batch_ptr = wa_bb_fn[i](engine, batch_ptr); in lrc_init_wa_ctx()
1655 err = i915_inject_probe_error(engine->i915, -ENODEV); in lrc_init_wa_ctx()
1669 i915_vma_put(engine->wa_ctx.vma); in lrc_init_wa_ctx()