Lines Matching refs:iir
233 i915_reg_t iir, i915_reg_t ier) in gen3_irq_reset() argument
241 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
242 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
243 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
244 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
299 i915_reg_t iir) in gen3_irq_init() argument
301 gen3_assert_iir_is_zero(uncore, iir); in gen3_irq_init()
1430 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i9xx_pipestat_irq_ack() argument
1468 if (iir & iir_bit) in i9xx_pipestat_irq_ack()
1496 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) in i8xx_pipestat_irq_handler() argument
1513 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i915_pipestat_irq_handler() argument
1532 if (blc_event || (iir & I915_ASLE_INTERRUPT)) in i915_pipestat_irq_handler()
1537 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i965_pipestat_irq_handler() argument
1556 if (blc_event || (iir & I915_ASLE_INTERRUPT)) in i965_pipestat_irq_handler()
1663 u32 iir, gt_iir, pm_iir; in valleyview_irq_handler() local
1670 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in valleyview_irq_handler()
1672 if (gt_iir == 0 && pm_iir == 0 && iir == 0) in valleyview_irq_handler()
1699 if (iir & I915_DISPLAY_PORT_INTERRUPT) in valleyview_irq_handler()
1704 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in valleyview_irq_handler()
1706 if (iir & (I915_LPE_PIPE_A_INTERRUPT | in valleyview_irq_handler()
1714 if (iir) in valleyview_irq_handler()
1715 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); in valleyview_irq_handler()
1750 u32 master_ctl, iir; in cherryview_irq_handler() local
1756 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in cherryview_irq_handler()
1758 if (master_ctl == 0 && iir == 0) in cherryview_irq_handler()
1782 if (iir & I915_DISPLAY_PORT_INTERRUPT) in cherryview_irq_handler()
1787 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in cherryview_irq_handler()
1789 if (iir & (I915_LPE_PIPE_A_INTERRUPT | in cherryview_irq_handler()
1798 if (iir) in cherryview_irq_handler()
1799 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); in cherryview_irq_handler()
2245 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) in gen11_hpd_irq_handler() argument
2248 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; in gen11_hpd_irq_handler()
2249 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; in gen11_hpd_irq_handler()
2279 "Unexpected DE HPD interrupt 0x%08x\n", iir); in gen11_hpd_irq_handler()
2335 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) in gen8_de_misc_irq_handler() argument
2339 if (iir & GEN8_DE_MISC_GSE) { in gen8_de_misc_irq_handler()
2344 if (iir & GEN8_DE_EDP_PSR) { in gen8_de_misc_irq_handler()
2455 u32 iir; in gen8_de_irq_handler() local
2461 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); in gen8_de_irq_handler()
2462 if (iir) { in gen8_de_irq_handler()
2463 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir); in gen8_de_irq_handler()
2465 gen8_de_misc_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2473 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR); in gen8_de_irq_handler()
2474 if (iir) { in gen8_de_irq_handler()
2475 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir); in gen8_de_irq_handler()
2477 gen11_hpd_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2485 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR); in gen8_de_irq_handler()
2486 if (iir) { in gen8_de_irq_handler()
2489 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir); in gen8_de_irq_handler()
2492 if (iir & gen8_de_port_aux_mask(dev_priv)) { in gen8_de_irq_handler()
2498 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; in gen8_de_irq_handler()
2505 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK; in gen8_de_irq_handler()
2514 (iir & BXT_DE_PORT_GMBUS)) { in gen8_de_irq_handler()
2520 u32 te_trigger = iir & (DSI0_TE | DSI1_TE); in gen8_de_irq_handler()
2543 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); in gen8_de_irq_handler()
2544 if (!iir) { in gen8_de_irq_handler()
2551 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); in gen8_de_irq_handler()
2553 if (iir & GEN8_PIPE_VBLANK) in gen8_de_irq_handler()
2556 if (iir & gen8_de_pipe_flip_done_mask(dev_priv)) in gen8_de_irq_handler()
2559 if (iir & GEN8_PIPE_CDCLK_CRC_DONE) in gen8_de_irq_handler()
2562 if (iir & gen8_de_pipe_underrun_mask(dev_priv)) in gen8_de_irq_handler()
2565 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); in gen8_de_irq_handler()
2580 iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); in gen8_de_irq_handler()
2581 if (iir) { in gen8_de_irq_handler()
2582 intel_uncore_write(&dev_priv->uncore, SDEIIR, iir); in gen8_de_irq_handler()
2586 icp_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2588 spt_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2590 cpt_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2658 u32 iir; in gen11_gu_misc_irq_ack() local
2663 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR); in gen11_gu_misc_irq_ack()
2664 if (likely(iir)) in gen11_gu_misc_irq_ack()
2665 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir); in gen11_gu_misc_irq_ack()
2667 return iir; in gen11_gu_misc_irq_ack()
2671 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir) in gen11_gu_misc_irq_handler() argument
2673 if (iir & GEN11_GU_MISC_GSE) in gen11_gu_misc_irq_handler()
4054 u16 iir; in i8xx_irq_handler() local
4056 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR); in i8xx_irq_handler()
4057 if (iir == 0) in i8xx_irq_handler()
4064 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i8xx_irq_handler()
4066 if (iir & I915_MASTER_ERROR_INTERRUPT) in i8xx_irq_handler()
4069 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); in i8xx_irq_handler()
4071 if (iir & I915_USER_INTERRUPT) in i8xx_irq_handler()
4072 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); in i8xx_irq_handler()
4074 if (iir & I915_MASTER_ERROR_INTERRUPT) in i8xx_irq_handler()
4077 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i8xx_irq_handler()
4158 u32 iir; in i915_irq_handler() local
4160 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i915_irq_handler()
4161 if (iir == 0) in i915_irq_handler()
4167 iir & I915_DISPLAY_PORT_INTERRUPT) in i915_irq_handler()
4172 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i915_irq_handler()
4174 if (iir & I915_MASTER_ERROR_INTERRUPT) in i915_irq_handler()
4177 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); in i915_irq_handler()
4179 if (iir & I915_USER_INTERRUPT) in i915_irq_handler()
4180 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir); in i915_irq_handler()
4182 if (iir & I915_MASTER_ERROR_INTERRUPT) in i915_irq_handler()
4188 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i915_irq_handler()
4304 u32 iir; in i965_irq_handler() local
4306 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i965_irq_handler()
4307 if (iir == 0) in i965_irq_handler()
4312 if (iir & I915_DISPLAY_PORT_INTERRUPT) in i965_irq_handler()
4317 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i965_irq_handler()
4319 if (iir & I915_MASTER_ERROR_INTERRUPT) in i965_irq_handler()
4322 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); in i965_irq_handler()
4324 if (iir & I915_USER_INTERRUPT) in i965_irq_handler()
4326 iir); in i965_irq_handler()
4328 if (iir & I915_BSD_USER_INTERRUPT) in i965_irq_handler()
4330 iir >> 25); in i965_irq_handler()
4332 if (iir & I915_MASTER_ERROR_INTERRUPT) in i965_irq_handler()
4338 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i965_irq_handler()