Lines Matching refs:uncore
232 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, in gen3_irq_reset() argument
235 intel_uncore_write(uncore, imr, 0xffffffff); in gen3_irq_reset()
236 intel_uncore_posting_read(uncore, imr); in gen3_irq_reset()
238 intel_uncore_write(uncore, ier, 0); in gen3_irq_reset()
241 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
242 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
243 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
244 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
247 void gen2_irq_reset(struct intel_uncore *uncore) in gen2_irq_reset() argument
249 intel_uncore_write16(uncore, GEN2_IMR, 0xffff); in gen2_irq_reset()
250 intel_uncore_posting_read16(uncore, GEN2_IMR); in gen2_irq_reset()
252 intel_uncore_write16(uncore, GEN2_IER, 0); in gen2_irq_reset()
255 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); in gen2_irq_reset()
256 intel_uncore_posting_read16(uncore, GEN2_IIR); in gen2_irq_reset()
257 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); in gen2_irq_reset()
258 intel_uncore_posting_read16(uncore, GEN2_IIR); in gen2_irq_reset()
264 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) in gen3_assert_iir_is_zero() argument
266 u32 val = intel_uncore_read(uncore, reg); in gen3_assert_iir_is_zero()
271 drm_WARN(&uncore->i915->drm, 1, in gen3_assert_iir_is_zero()
274 intel_uncore_write(uncore, reg, 0xffffffff); in gen3_assert_iir_is_zero()
275 intel_uncore_posting_read(uncore, reg); in gen3_assert_iir_is_zero()
276 intel_uncore_write(uncore, reg, 0xffffffff); in gen3_assert_iir_is_zero()
277 intel_uncore_posting_read(uncore, reg); in gen3_assert_iir_is_zero()
280 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore) in gen2_assert_iir_is_zero() argument
282 u16 val = intel_uncore_read16(uncore, GEN2_IIR); in gen2_assert_iir_is_zero()
287 drm_WARN(&uncore->i915->drm, 1, in gen2_assert_iir_is_zero()
290 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); in gen2_assert_iir_is_zero()
291 intel_uncore_posting_read16(uncore, GEN2_IIR); in gen2_assert_iir_is_zero()
292 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); in gen2_assert_iir_is_zero()
293 intel_uncore_posting_read16(uncore, GEN2_IIR); in gen2_assert_iir_is_zero()
296 void gen3_irq_init(struct intel_uncore *uncore, in gen3_irq_init() argument
301 gen3_assert_iir_is_zero(uncore, iir); in gen3_irq_init()
303 intel_uncore_write(uncore, ier, ier_val); in gen3_irq_init()
304 intel_uncore_write(uncore, imr, imr_val); in gen3_irq_init()
305 intel_uncore_posting_read(uncore, imr); in gen3_irq_init()
308 void gen2_irq_init(struct intel_uncore *uncore, in gen2_irq_init() argument
311 gen2_assert_iir_is_zero(uncore); in gen2_irq_init()
313 intel_uncore_write16(uncore, GEN2_IER, ier_val); in gen2_irq_init()
314 intel_uncore_write16(uncore, GEN2_IMR, imr_val); in gen2_irq_init()
315 intel_uncore_posting_read16(uncore, GEN2_IMR); in gen2_irq_init()
329 val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN); in i915_hotplug_interrupt_update_locked()
332 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val); in i915_hotplug_interrupt_update_locked()
377 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
378 intel_uncore_posting_read(&dev_priv->uncore, DEIMR); in ilk_update_display_irq()
412 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
419 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val); in bdw_update_port_irq()
420 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
450 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
451 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
477 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); in ibx_display_interrupt_update()
488 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr); in ibx_display_interrupt_update()
489 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR); in ibx_display_interrupt_update()
565 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); in i915_enable_pipestat()
566 intel_uncore_posting_read(&dev_priv->uncore, reg); in i915_enable_pipestat()
588 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); in i915_disable_pipestat()
589 intel_uncore_posting_read(&dev_priv->uncore, reg); in i915_disable_pipestat()
711 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_vblank_counter()
724 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_vblank_counter()
747 return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe)); in g4x_get_vblank_counter()
917 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
985 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
1023 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
1025 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
1059 misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL); in ivb_parity_work()
1060 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in ivb_parity_work()
1061 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); in ivb_parity_work()
1075 error_status = intel_uncore_read(&dev_priv->uncore, reg); in ivb_parity_work()
1080 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); in ivb_parity_work()
1081 intel_uncore_posting_read(&dev_priv->uncore, reg); in ivb_parity_work()
1102 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); in ivb_parity_work()
1379 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in hsw_pipe_crc_irq_handler()
1387 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1388 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1389 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1390 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1391 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
1400 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe)); in i9xx_pipe_crc_irq_handler()
1405 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe)); in i9xx_pipe_crc_irq_handler()
1410 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)), in i9xx_pipe_crc_irq_handler()
1411 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)), in i9xx_pipe_crc_irq_handler()
1412 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), in i9xx_pipe_crc_irq_handler()
1421 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe), in i9xx_pipestat_irq_reset()
1475 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; in i9xx_pipestat_irq_ack()
1488 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); in i9xx_pipestat_irq_ack()
1489 intel_uncore_write(&dev_priv->uncore, reg, enable_mask); in i9xx_pipestat_irq_ack()
1608 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask; in i9xx_hpd_irq_ack()
1614 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status); in i9xx_hpd_irq_ack()
1619 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); in i9xx_hpd_irq_ack()
1668 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); in valleyview_irq_handler()
1669 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); in valleyview_irq_handler()
1670 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in valleyview_irq_handler()
1690 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); in valleyview_irq_handler()
1691 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER); in valleyview_irq_handler()
1692 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0); in valleyview_irq_handler()
1695 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir); in valleyview_irq_handler()
1697 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); in valleyview_irq_handler()
1715 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); in valleyview_irq_handler()
1717 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); in valleyview_irq_handler()
1718 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); in valleyview_irq_handler()
1755 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; in cherryview_irq_handler()
1756 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in cherryview_irq_handler()
1776 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_handler()
1777 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER); in cherryview_irq_handler()
1778 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0); in cherryview_irq_handler()
1799 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); in cherryview_irq_handler()
1801 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); in cherryview_irq_handler()
1802 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_handler()
1828 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in ibx_hpd_irq_handler()
1837 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); in ibx_hpd_irq_handler()
1882 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in ibx_irq_handler()
1901 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT); in ivb_err_int_handler()
1919 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int); in ivb_err_int_handler()
1924 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT); in cpt_serr_int_handler()
1934 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int); in cpt_serr_int_handler()
1967 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in cpt_irq_handler()
1983 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI); in icp_irq_handler()
1984 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg); in icp_irq_handler()
1995 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC); in icp_irq_handler()
1996 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg); in icp_irq_handler()
2021 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in spt_irq_handler()
2022 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); in spt_irq_handler()
2033 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2); in spt_irq_handler()
2034 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg); in spt_irq_handler()
2054 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL); in ilk_hpd_irq_handler()
2055 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); in ilk_hpd_irq_handler()
2099 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); in ilk_display_irq_handler()
2107 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); in ilk_display_irq_handler()
2142 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); in ivb_display_irq_handler()
2147 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); in ivb_display_irq_handler()
2162 void __iomem * const regs = i915->uncore.regs; in ilk_irq_handler()
2234 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in bxt_hpd_irq_handler()
2235 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); in bxt_hpd_irq_handler()
2254 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL); in gen11_hpd_irq_handler()
2255 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg); in gen11_hpd_irq_handler()
2266 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL); in gen11_hpd_irq_handler()
2267 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg); in gen11_hpd_irq_handler()
2357 psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg); in gen8_de_misc_irq_handler()
2358 intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir); in gen8_de_misc_irq_handler()
2387 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); in gen11_dsi_te_interrupt_handler()
2399 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans)); in gen11_dsi_te_interrupt_handler()
2408 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans)); in gen11_dsi_te_interrupt_handler()
2428 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port)); in gen11_dsi_te_interrupt_handler()
2429 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); in gen11_dsi_te_interrupt_handler()
2461 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); in gen8_de_irq_handler()
2463 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir); in gen8_de_irq_handler()
2473 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR); in gen8_de_irq_handler()
2475 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir); in gen8_de_irq_handler()
2485 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR); in gen8_de_irq_handler()
2489 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir); in gen8_de_irq_handler()
2543 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); in gen8_de_irq_handler()
2551 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); in gen8_de_irq_handler()
2580 iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); in gen8_de_irq_handler()
2582 intel_uncore_write(&dev_priv->uncore, SDEIIR, iir); in gen8_de_irq_handler()
2625 void __iomem * const regs = dev_priv->uncore.regs; in gen8_irq_handler()
2657 void __iomem * const regs = gt->uncore->regs; in gen11_gu_misc_irq_ack()
2698 void __iomem * const regs = i915->uncore.regs; in gen11_display_irq_handler()
2717 void __iomem * const regs = i915->uncore.regs; in gen11_irq_handler()
2775 void __iomem * const regs = i915->uncore.regs; in dg1_irq_handler()
2841 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); in i915gm_enable_vblank()
2898 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port)); in gen11_dsi_configure_te()
2904 intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp); in gen11_dsi_configure_te()
2906 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port)); in gen11_dsi_configure_te()
2907 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); in gen11_dsi_configure_te()
2956 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)… in i915gm_disable_vblank()
3001 struct intel_uncore *uncore = &dev_priv->uncore; in ibx_irq_reset() local
3006 GEN3_IRQ_RESET(uncore, SDE); in ibx_irq_reset()
3009 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff); in ibx_irq_reset()
3014 struct intel_uncore *uncore = &dev_priv->uncore; in vlv_display_irq_reset() local
3017 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); in vlv_display_irq_reset()
3019 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK); in vlv_display_irq_reset()
3022 …intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_ST… in vlv_display_irq_reset()
3026 GEN3_IRQ_RESET(uncore, VLV_); in vlv_display_irq_reset()
3032 struct intel_uncore *uncore = &dev_priv->uncore; in vlv_display_irq_postinstall() local
3058 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); in vlv_display_irq_postinstall()
3065 struct intel_uncore *uncore = &dev_priv->uncore; in ilk_irq_reset() local
3067 GEN3_IRQ_RESET(uncore, DE); in ilk_irq_reset()
3071 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff); in ilk_irq_reset()
3074 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); in ilk_irq_reset()
3075 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); in ilk_irq_reset()
3085 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); in valleyview_irq_reset()
3086 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); in valleyview_irq_reset()
3098 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_display_irq_reset() local
3104 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); in gen8_display_irq_reset()
3105 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); in gen8_display_irq_reset()
3110 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); in gen8_display_irq_reset()
3112 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); in gen8_display_irq_reset()
3113 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); in gen8_display_irq_reset()
3118 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_reset() local
3120 gen8_master_intr_disable(dev_priv->uncore.regs); in gen8_irq_reset()
3124 GEN3_IRQ_RESET(uncore, GEN8_PCU_); in gen8_irq_reset()
3133 struct intel_uncore *uncore = &dev_priv->uncore; in gen11_display_irq_reset() local
3141 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0); in gen11_display_irq_reset()
3153 intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff); in gen11_display_irq_reset()
3154 intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff); in gen11_display_irq_reset()
3157 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); in gen11_display_irq_reset()
3158 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); in gen11_display_irq_reset()
3164 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); in gen11_display_irq_reset()
3166 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); in gen11_display_irq_reset()
3167 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); in gen11_display_irq_reset()
3168 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_); in gen11_display_irq_reset()
3171 GEN3_IRQ_RESET(uncore, SDE); in gen11_display_irq_reset()
3176 struct intel_uncore *uncore = &dev_priv->uncore; in gen11_irq_reset() local
3178 gen11_master_intr_disable(dev_priv->uncore.regs); in gen11_irq_reset()
3183 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); in gen11_irq_reset()
3184 GEN3_IRQ_RESET(uncore, GEN8_PCU_); in gen11_irq_reset()
3189 struct intel_uncore *uncore = &dev_priv->uncore; in dg1_irq_reset() local
3191 dg1_master_intr_disable(dev_priv->uncore.regs); in dg1_irq_reset()
3196 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); in dg1_irq_reset()
3197 GEN3_IRQ_RESET(uncore, GEN8_PCU_); in dg1_irq_reset()
3203 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_power_well_post_enable() local
3217 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, in gen8_irq_power_well_post_enable()
3227 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_power_well_pre_disable() local
3238 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); in gen8_irq_power_well_pre_disable()
3248 struct intel_uncore *uncore = &dev_priv->uncore; in cherryview_irq_reset() local
3250 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_reset()
3251 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_reset()
3255 GEN3_IRQ_RESET(uncore, GEN8_PCU_); in cherryview_irq_reset()
3297 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in ibx_hpd_detection_setup()
3306 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); in ibx_hpd_detection_setup()
3355 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI); in icp_ddi_hpd_detection_setup()
3361 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug); in icp_ddi_hpd_detection_setup()
3368 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC); in icp_tc_hpd_detection_setup()
3376 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug); in icp_tc_hpd_detection_setup()
3387 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); in icp_hpd_irq_setup()
3415 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1); in dg1_hpd_irq_setup()
3420 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val); in dg1_hpd_irq_setup()
3429 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL); in gen11_tc_hpd_detection_setup()
3437 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug); in gen11_tc_hpd_detection_setup()
3444 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL); in gen11_tbt_hpd_detection_setup()
3452 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug); in gen11_tbt_hpd_detection_setup()
3463 val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); in gen11_hpd_irq_setup()
3466 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val); in gen11_hpd_irq_setup()
3467 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); in gen11_hpd_irq_setup()
3510 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1); in spt_hpd_detection_setup()
3513 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val); in spt_hpd_detection_setup()
3517 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in spt_hpd_detection_setup()
3523 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); in spt_hpd_detection_setup()
3525 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2); in spt_hpd_detection_setup()
3528 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug); in spt_hpd_detection_setup()
3536 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); in spt_hpd_irq_setup()
3567 hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL); in ilk_hpd_detection_setup()
3571 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); in ilk_hpd_detection_setup()
3621 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in bxt_hpd_detection_setup()
3629 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); in bxt_hpd_detection_setup()
3657 struct intel_uncore *uncore = &dev_priv->uncore; in ibx_irq_postinstall() local
3670 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); in ibx_irq_postinstall()
3675 struct intel_uncore *uncore = &dev_priv->uncore; in ilk_irq_postinstall() local
3699 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); in ilk_irq_postinstall()
3712 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, in ilk_irq_postinstall()
3754 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); in valleyview_irq_postinstall()
3755 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); in valleyview_irq_postinstall()
3760 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_de_irq_postinstall() local
3809 gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans)); in gen8_de_irq_postinstall()
3812 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); in gen8_de_irq_postinstall()
3820 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, in gen8_de_irq_postinstall()
3825 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables); in gen8_de_irq_postinstall()
3826 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); in gen8_de_irq_postinstall()
3833 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, in gen8_de_irq_postinstall()
3840 struct intel_uncore *uncore = &dev_priv->uncore; in icp_irq_postinstall() local
3843 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); in icp_irq_postinstall()
3856 gen8_master_intr_enable(dev_priv->uncore.regs); in gen8_irq_postinstall()
3866 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, in gen11_de_irq_postinstall()
3872 struct intel_uncore *uncore = &dev_priv->uncore; in gen11_irq_postinstall() local
3881 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); in gen11_irq_postinstall()
3883 gen11_master_intr_enable(uncore->regs); in gen11_irq_postinstall()
3884 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ); in gen11_irq_postinstall()
3889 struct intel_uncore *uncore = &dev_priv->uncore; in dg1_irq_postinstall() local
3894 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); in dg1_irq_postinstall()
3899 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, in dg1_irq_postinstall()
3903 dg1_master_intr_enable(dev_priv->uncore.regs); in dg1_irq_postinstall()
3904 intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR); in dg1_irq_postinstall()
3916 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_postinstall()
3917 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_postinstall()
3922 struct intel_uncore *uncore = &dev_priv->uncore; in i8xx_irq_reset() local
3926 GEN2_IRQ_RESET(uncore); in i8xx_irq_reset()
3932 struct intel_uncore *uncore = &dev_priv->uncore; in i8xx_irq_postinstall() local
3935 intel_uncore_write16(uncore, in i8xx_irq_postinstall()
3952 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask); in i8xx_irq_postinstall()
3965 struct intel_uncore *uncore = &i915->uncore; in i8xx_error_irq_ack() local
3968 *eir = intel_uncore_read16(uncore, EIR); in i8xx_error_irq_ack()
3971 intel_uncore_write16(uncore, EIR, *eir); in i8xx_error_irq_ack()
3973 *eir_stuck = intel_uncore_read16(uncore, EIR); in i8xx_error_irq_ack()
3987 emr = intel_uncore_read16(uncore, EMR); in i8xx_error_irq_ack()
3988 intel_uncore_write16(uncore, EMR, 0xffff); in i8xx_error_irq_ack()
3989 intel_uncore_write16(uncore, EMR, emr | *eir_stuck); in i8xx_error_irq_ack()
4007 *eir = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
4009 intel_uncore_write(&dev_priv->uncore, EIR, *eir); in i9xx_error_irq_ack()
4011 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
4025 emr = intel_uncore_read(&dev_priv->uncore, EMR); in i9xx_error_irq_ack()
4026 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff); in i9xx_error_irq_ack()
4027 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck); in i9xx_error_irq_ack()
4056 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR); in i8xx_irq_handler()
4069 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); in i8xx_irq_handler()
4089 struct intel_uncore *uncore = &dev_priv->uncore; in i915_irq_reset() local
4093 …intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT… in i915_irq_reset()
4098 GEN3_IRQ_RESET(uncore, GEN2_); in i915_irq_reset()
4104 struct intel_uncore *uncore = &dev_priv->uncore; in i915_irq_postinstall() local
4107 intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE | in i915_irq_postinstall()
4131 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); in i915_irq_postinstall()
4160 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i915_irq_handler()
4177 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); in i915_irq_handler()
4200 struct intel_uncore *uncore = &dev_priv->uncore; in i965_irq_reset() local
4203 …intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT… in i965_irq_reset()
4207 GEN3_IRQ_RESET(uncore, GEN2_); in i965_irq_reset()
4213 struct intel_uncore *uncore = &dev_priv->uncore; in i965_irq_postinstall() local
4230 intel_uncore_write(&dev_priv->uncore, EMR, error_mask); in i965_irq_postinstall()
4251 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); in i965_irq_postinstall()
4306 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i965_irq_handler()
4322 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); in i965_irq_handler()