Lines Matching refs:gpu_write
124 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
125 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010); in a3xx_hw_init()
126 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
127 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
128 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
129 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
130 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010); in a3xx_hw_init()
132 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff); in a3xx_hw_init()
134 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
136 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); in a3xx_hw_init()
137 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c); in a3xx_hw_init()
139 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); in a3xx_hw_init()
140 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a); in a3xx_hw_init()
141 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a); in a3xx_hw_init()
144 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
145 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010); in a3xx_hw_init()
146 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
147 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
148 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
149 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
150 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010); in a3xx_hw_init()
152 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff); in a3xx_hw_init()
154 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
156 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); in a3xx_hw_init()
157 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c); in a3xx_hw_init()
159 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff); in a3xx_hw_init()
160 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4); in a3xx_hw_init()
169 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f); in a3xx_hw_init()
170 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4); in a3xx_hw_init()
172 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f); in a3xx_hw_init()
173 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
175 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); in a3xx_hw_init()
179 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818); in a3xx_hw_init()
180 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818); in a3xx_hw_init()
181 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818); in a3xx_hw_init()
182 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x18181818); in a3xx_hw_init()
183 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
184 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x18181818); in a3xx_hw_init()
185 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x18181818); in a3xx_hw_init()
187 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f); in a3xx_hw_init()
189 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
191 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001); in a3xx_hw_init()
193 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003f); in a3xx_hw_init()
194 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003f003f); in a3xx_hw_init()
196 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f); in a3xx_hw_init()
197 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4); in a3xx_hw_init()
201 gpu_write(gpu, REG_A3XX_VBIF_CLKON, 0x00000001); in a3xx_hw_init()
208 gpu_write(gpu, REG_A3XX_RBBM_GPU_BUSY_MASKED, 0xffffffff); in a3xx_hw_init()
211 gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10); in a3xx_hw_init()
212 gpu_write(gpu, REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10); in a3xx_hw_init()
217 gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL0, 0x00000001); in a3xx_hw_init()
220 gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL1, 0xa6ffffff); in a3xx_hw_init()
223 gpu_write(gpu, REG_A3XX_RBBM_RBBM_CTL, 0x00030000); in a3xx_hw_init()
228 gpu_write(gpu, REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL, 0x00010fff); in a3xx_hw_init()
231 gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001); in a3xx_hw_init()
235 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); in a3xx_hw_init()
237 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff); in a3xx_hw_init()
239 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); in a3xx_hw_init()
241 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbffcffff); in a3xx_hw_init()
244 gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x05515455); in a3xx_hw_init()
246 gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x00000000); in a3xx_hw_init()
250 gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR, in a3xx_hw_init()
255 gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01); in a3xx_hw_init()
260 gpu_write(gpu, perfcntr->select_reg, perfcntr->select_val); in a3xx_hw_init()
263 gpu_write(gpu, REG_A3XX_RBBM_INT_0_MASK, A3XX_INT0_MASK); in a3xx_hw_init()
273 gpu_write(gpu, REG_AXXX_CP_RB_CNTL, in a3xx_hw_init()
277 gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova)); in a3xx_hw_init()
280 gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007); in a3xx_hw_init()
283 gpu_write(gpu, REG_A3XX_CP_PROTECT(0), 0x63000040); in a3xx_hw_init()
284 gpu_write(gpu, REG_A3XX_CP_PROTECT(1), 0x62000080); in a3xx_hw_init()
285 gpu_write(gpu, REG_A3XX_CP_PROTECT(2), 0x600000cc); in a3xx_hw_init()
286 gpu_write(gpu, REG_A3XX_CP_PROTECT(3), 0x60000108); in a3xx_hw_init()
287 gpu_write(gpu, REG_A3XX_CP_PROTECT(4), 0x64000140); in a3xx_hw_init()
288 gpu_write(gpu, REG_A3XX_CP_PROTECT(5), 0x66000400); in a3xx_hw_init()
291 gpu_write(gpu, REG_A3XX_CP_PROTECT(6), 0x65000700); in a3xx_hw_init()
292 gpu_write(gpu, REG_A3XX_CP_PROTECT(7), 0x610007d8); in a3xx_hw_init()
293 gpu_write(gpu, REG_A3XX_CP_PROTECT(8), 0x620007e0); in a3xx_hw_init()
294 gpu_write(gpu, REG_A3XX_CP_PROTECT(9), 0x61001178); in a3xx_hw_init()
295 gpu_write(gpu, REG_A3XX_CP_PROTECT(10), 0x64001180); in a3xx_hw_init()
298 gpu_write(gpu, REG_A3XX_CP_PROTECT(11), 0x60003300); in a3xx_hw_init()
301 gpu_write(gpu, REG_A3XX_CP_PROTECT(12), 0x6b00c000); in a3xx_hw_init()
314 gpu_write(gpu, REG_AXXX_CP_DEBUG, in a3xx_hw_init()
317 gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0); in a3xx_hw_init()
319 gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]); in a3xx_hw_init()
326 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0); in a3xx_hw_init()
328 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]); in a3xx_hw_init()
333 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, in a3xx_hw_init()
343 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x003e2008); in a3xx_hw_init()
347 gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0); in a3xx_hw_init()
367 gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1); in a3xx_recover()
369 gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0); in a3xx_recover()
414 gpu_write(gpu, REG_A3XX_RBBM_INT_CLEAR_CMD, status); in a3xx_irq()