Lines Matching refs:val
121 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR() argument
123 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; in MDP4_VERSION_MINOR()
127 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR() argument
129 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; in MDP4_VERSION_MAJOR()
149 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM() argument
151 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; in MDP4_DISP_INTF_SEL_PRIM()
155 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC() argument
157 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; in MDP4_DISP_INTF_SEL_SEC()
161 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT() argument
163 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; in MDP4_DISP_INTF_SEL_EXT()
191 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE0() argument
193 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK; in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
198 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE1() argument
200 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK; in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
205 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE2() argument
207 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK; in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
212 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE3() argument
214 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK; in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
219 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE4() argument
221 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK; in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
226 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE5() argument
228 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK; in MDP4_LAYERMIXER2_IN_CFG_PIPE5()
233 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE6() argument
235 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK; in MDP4_LAYERMIXER2_IN_CFG_PIPE6()
240 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE7() argument
242 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK; in MDP4_LAYERMIXER2_IN_CFG_PIPE7()
251 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER_IN_CFG_PIPE0() argument
253 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK; in MDP4_LAYERMIXER_IN_CFG_PIPE0()
258 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER_IN_CFG_PIPE1() argument
260 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK; in MDP4_LAYERMIXER_IN_CFG_PIPE1()
265 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER_IN_CFG_PIPE2() argument
267 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK; in MDP4_LAYERMIXER_IN_CFG_PIPE2()
272 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER_IN_CFG_PIPE3() argument
274 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK; in MDP4_LAYERMIXER_IN_CFG_PIPE3()
279 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER_IN_CFG_PIPE4() argument
281 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK; in MDP4_LAYERMIXER_IN_CFG_PIPE4()
286 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER_IN_CFG_PIPE5() argument
288 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK; in MDP4_LAYERMIXER_IN_CFG_PIPE5()
293 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER_IN_CFG_PIPE6() argument
295 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK; in MDP4_LAYERMIXER_IN_CFG_PIPE6()
300 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER_IN_CFG_PIPE7() argument
302 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK; in MDP4_LAYERMIXER_IN_CFG_PIPE7()
334 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val) in MDP4_OVLP_SIZE_HEIGHT() argument
336 return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK; in MDP4_OVLP_SIZE_HEIGHT()
340 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val) in MDP4_OVLP_SIZE_WIDTH() argument
342 return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK; in MDP4_OVLP_SIZE_WIDTH()
366 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) in MDP4_OVLP_STAGE_OP_FG_ALPHA() argument
368 return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK; in MDP4_OVLP_STAGE_OP_FG_ALPHA()
374 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) in MDP4_OVLP_STAGE_OP_BG_ALPHA() argument
376 return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK; in MDP4_OVLP_STAGE_OP_BG_ALPHA()
469 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) in MDP4_DMA_CONFIG_G_BPC() argument
471 return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK; in MDP4_DMA_CONFIG_G_BPC()
475 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) in MDP4_DMA_CONFIG_B_BPC() argument
477 return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK; in MDP4_DMA_CONFIG_B_BPC()
481 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) in MDP4_DMA_CONFIG_R_BPC() argument
483 return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK; in MDP4_DMA_CONFIG_R_BPC()
488 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val) in MDP4_DMA_CONFIG_PACK() argument
490 return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK; in MDP4_DMA_CONFIG_PACK()
498 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) in MDP4_DMA_SRC_SIZE_HEIGHT() argument
500 return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK; in MDP4_DMA_SRC_SIZE_HEIGHT()
504 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) in MDP4_DMA_SRC_SIZE_WIDTH() argument
506 return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK; in MDP4_DMA_SRC_SIZE_WIDTH()
516 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) in MDP4_DMA_DST_SIZE_HEIGHT() argument
518 return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK; in MDP4_DMA_DST_SIZE_HEIGHT()
522 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) in MDP4_DMA_DST_SIZE_WIDTH() argument
524 return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK; in MDP4_DMA_DST_SIZE_WIDTH()
530 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) in MDP4_DMA_CURSOR_SIZE_WIDTH() argument
532 return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK; in MDP4_DMA_CURSOR_SIZE_WIDTH()
536 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) in MDP4_DMA_CURSOR_SIZE_HEIGHT() argument
538 return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK; in MDP4_DMA_CURSOR_SIZE_HEIGHT()
546 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val) in MDP4_DMA_CURSOR_POS_X() argument
548 return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK; in MDP4_DMA_CURSOR_POS_X()
552 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val) in MDP4_DMA_CURSOR_POS_Y() argument
554 return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK; in MDP4_DMA_CURSOR_POS_Y()
561 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT() argument
563 …return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT… in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()
603 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) in MDP4_PIPE_SRC_SIZE_HEIGHT() argument
605 return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK; in MDP4_PIPE_SRC_SIZE_HEIGHT()
609 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) in MDP4_PIPE_SRC_SIZE_WIDTH() argument
611 return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK; in MDP4_PIPE_SRC_SIZE_WIDTH()
617 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val) in MDP4_PIPE_SRC_XY_Y() argument
619 return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK; in MDP4_PIPE_SRC_XY_Y()
623 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val) in MDP4_PIPE_SRC_XY_X() argument
625 return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK; in MDP4_PIPE_SRC_XY_X()
631 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) in MDP4_PIPE_DST_SIZE_HEIGHT() argument
633 return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK; in MDP4_PIPE_DST_SIZE_HEIGHT()
637 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) in MDP4_PIPE_DST_SIZE_WIDTH() argument
639 return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK; in MDP4_PIPE_DST_SIZE_WIDTH()
645 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val) in MDP4_PIPE_DST_XY_Y() argument
647 return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK; in MDP4_PIPE_DST_XY_Y()
651 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val) in MDP4_PIPE_DST_XY_X() argument
653 return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK; in MDP4_PIPE_DST_XY_X()
667 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) in MDP4_PIPE_SRC_STRIDE_A_P0() argument
669 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK; in MDP4_PIPE_SRC_STRIDE_A_P0()
673 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) in MDP4_PIPE_SRC_STRIDE_A_P1() argument
675 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK; in MDP4_PIPE_SRC_STRIDE_A_P1()
681 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) in MDP4_PIPE_SRC_STRIDE_B_P2() argument
683 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK; in MDP4_PIPE_SRC_STRIDE_B_P2()
687 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) in MDP4_PIPE_SRC_STRIDE_B_P3() argument
689 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK; in MDP4_PIPE_SRC_STRIDE_B_P3()
695 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val) in MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT() argument
697 …return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__… in MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT()
701 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val) in MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH() argument
703 …return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MA… in MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH()
709 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) in MDP4_PIPE_SRC_FORMAT_G_BPC() argument
711 return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK; in MDP4_PIPE_SRC_FORMAT_G_BPC()
715 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) in MDP4_PIPE_SRC_FORMAT_B_BPC() argument
717 return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK; in MDP4_PIPE_SRC_FORMAT_B_BPC()
721 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) in MDP4_PIPE_SRC_FORMAT_R_BPC() argument
723 return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK; in MDP4_PIPE_SRC_FORMAT_R_BPC()
727 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) in MDP4_PIPE_SRC_FORMAT_A_BPC() argument
729 return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK; in MDP4_PIPE_SRC_FORMAT_A_BPC()
734 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) in MDP4_PIPE_SRC_FORMAT_CPP() argument
736 return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK; in MDP4_PIPE_SRC_FORMAT_CPP()
741 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) in MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT() argument
743 …return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MA… in MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT()
749 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val) in MDP4_PIPE_SRC_FORMAT_FETCH_PLANES() argument
751 …return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MA… in MDP4_PIPE_SRC_FORMAT_FETCH_PLANES()
756 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP() argument
758 return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK; in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()
762 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val) in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT() argument
764 …return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MA… in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()
770 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) in MDP4_PIPE_SRC_UNPACK_ELEM0() argument
772 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK; in MDP4_PIPE_SRC_UNPACK_ELEM0()
776 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) in MDP4_PIPE_SRC_UNPACK_ELEM1() argument
778 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK; in MDP4_PIPE_SRC_UNPACK_ELEM1()
782 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) in MDP4_PIPE_SRC_UNPACK_ELEM2() argument
784 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK; in MDP4_PIPE_SRC_UNPACK_ELEM2()
788 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) in MDP4_PIPE_SRC_UNPACK_ELEM3() argument
790 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK; in MDP4_PIPE_SRC_UNPACK_ELEM3()
798 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val) in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL() argument
800 …return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MA… in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()
804 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val) in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL() argument
806 …return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MA… in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()
856 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) in MDP4_LCDC_HSYNC_CTRL_PULSEW() argument
858 return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK; in MDP4_LCDC_HSYNC_CTRL_PULSEW()
862 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) in MDP4_LCDC_HSYNC_CTRL_PERIOD() argument
864 return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK; in MDP4_LCDC_HSYNC_CTRL_PERIOD()
874 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) in MDP4_LCDC_DISPLAY_HCTRL_START() argument
876 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK; in MDP4_LCDC_DISPLAY_HCTRL_START()
880 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) in MDP4_LCDC_DISPLAY_HCTRL_END() argument
882 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK; in MDP4_LCDC_DISPLAY_HCTRL_END()
892 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) in MDP4_LCDC_ACTIVE_HCTL_START() argument
894 return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK; in MDP4_LCDC_ACTIVE_HCTL_START()
898 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) in MDP4_LCDC_ACTIVE_HCTL_END() argument
900 return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK; in MDP4_LCDC_ACTIVE_HCTL_END()
913 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) in MDP4_LCDC_UNDERFLOW_CLR_COLOR() argument
915 return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK; in MDP4_LCDC_UNDERFLOW_CLR_COLOR()
951 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0() argument
953 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__… in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0()
957 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1() argument
959 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__… in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1()
963 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2() argument
965 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__… in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2()
969 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3() argument
971 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__… in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3()
977 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4() argument
979 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__… in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4()
983 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5() argument
985 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__… in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5()
989 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6() argument
991 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__… in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6()
1030 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) in MDP4_DTV_HSYNC_CTRL_PULSEW() argument
1032 return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK; in MDP4_DTV_HSYNC_CTRL_PULSEW()
1036 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) in MDP4_DTV_HSYNC_CTRL_PERIOD() argument
1038 return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK; in MDP4_DTV_HSYNC_CTRL_PERIOD()
1048 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) in MDP4_DTV_DISPLAY_HCTRL_START() argument
1050 return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK; in MDP4_DTV_DISPLAY_HCTRL_START()
1054 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) in MDP4_DTV_DISPLAY_HCTRL_END() argument
1056 return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK; in MDP4_DTV_DISPLAY_HCTRL_END()
1066 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) in MDP4_DTV_ACTIVE_HCTL_START() argument
1068 return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK; in MDP4_DTV_ACTIVE_HCTL_START()
1072 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) in MDP4_DTV_ACTIVE_HCTL_END() argument
1074 return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK; in MDP4_DTV_ACTIVE_HCTL_END()
1087 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) in MDP4_DTV_UNDERFLOW_CLR_COLOR() argument
1089 return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK; in MDP4_DTV_UNDERFLOW_CLR_COLOR()
1109 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) in MDP4_DSI_HSYNC_CTRL_PULSEW() argument
1111 return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK; in MDP4_DSI_HSYNC_CTRL_PULSEW()
1115 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) in MDP4_DSI_HSYNC_CTRL_PERIOD() argument
1117 return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK; in MDP4_DSI_HSYNC_CTRL_PERIOD()
1127 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) in MDP4_DSI_DISPLAY_HCTRL_START() argument
1129 return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK; in MDP4_DSI_DISPLAY_HCTRL_START()
1133 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) in MDP4_DSI_DISPLAY_HCTRL_END() argument
1135 return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK; in MDP4_DSI_DISPLAY_HCTRL_END()
1145 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) in MDP4_DSI_ACTIVE_HCTL_START() argument
1147 return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK; in MDP4_DSI_ACTIVE_HCTL_START()
1151 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) in MDP4_DSI_ACTIVE_HCTL_END() argument
1153 return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK; in MDP4_DSI_ACTIVE_HCTL_END()
1166 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) in MDP4_DSI_UNDERFLOW_CLR_COLOR() argument
1168 return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK; in MDP4_DSI_UNDERFLOW_CLR_COLOR()