Lines Matching refs:msm_gpu
45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
46 int (*hw_init)(struct msm_gpu *gpu);
47 int (*pm_suspend)(struct msm_gpu *gpu);
48 int (*pm_resume)(struct msm_gpu *gpu);
49 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
50 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
51 irqreturn_t (*irq)(struct msm_gpu *irq);
52 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
53 void (*recover)(struct msm_gpu *gpu);
54 void (*destroy)(struct msm_gpu *gpu);
57 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
60 void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
62 unsigned long (*gpu_busy)(struct msm_gpu *gpu);
63 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
65 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
66 void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp);
68 (struct msm_gpu *gpu, struct platform_device *pdev);
70 (struct msm_gpu *gpu);
71 uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
124 struct msm_gpu { struct
223 static inline struct msm_gpu *dev_to_gpu(struct device *dev) in dev_to_gpu() argument
226 return container_of(adreno_smmu, struct msm_gpu, adreno_smmu); in dev_to_gpu()
237 static inline bool msm_gpu_active(struct msm_gpu *gpu) in msm_gpu_active()
329 static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio, in msm_gpu_convert_priority()
424 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) in gpu_write()
429 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) in gpu_read()
434 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) in gpu_rmw()
439 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi) in gpu_read64()
463 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) in gpu_write64()
470 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
471 int msm_gpu_pm_resume(struct msm_gpu *gpu);
500 void msm_devfreq_init(struct msm_gpu *gpu);
501 void msm_devfreq_cleanup(struct msm_gpu *gpu);
502 void msm_devfreq_resume(struct msm_gpu *gpu);
503 void msm_devfreq_suspend(struct msm_gpu *gpu);
504 void msm_devfreq_active(struct msm_gpu *gpu);
505 void msm_devfreq_idle(struct msm_gpu *gpu);
507 int msm_gpu_hw_init(struct msm_gpu *gpu);
509 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
510 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
511 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
514 void msm_gpu_retire(struct msm_gpu *gpu);
515 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
518 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
522 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
524 void msm_gpu_cleanup(struct msm_gpu *gpu);
526 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
536 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu) in msm_gpu_crashstate_get()
552 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu) in msm_gpu_crashstate_put()