Lines Matching refs:gr
28 tu102_gr_init_fecs_exceptions(struct gf100_gr *gr) in tu102_gr_init_fecs_exceptions() argument
30 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006f0002); in tu102_gr_init_fecs_exceptions()
34 tu102_gr_init_fs(struct gf100_gr *gr) in tu102_gr_init_fs() argument
36 struct nvkm_device *device = gr->base.engine.subdev.device; in tu102_gr_init_fs()
39 gp100_grctx_generate_smid_config(gr); in tu102_gr_init_fs()
40 gk104_grctx_generate_gpc_tpc_nr(gr); in tu102_gr_init_fs()
42 for (sm = 0; sm < gr->sm_nr; sm++) { in tu102_gr_init_fs()
43 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + in tu102_gr_init_fs()
44 gr->sm[sm].tpc * 4), sm); in tu102_gr_init_fs()
47 gm200_grctx_generate_dist_skip_table(gr); in tu102_gr_init_fs()
48 gf100_gr_init_num_tpc_per_gpc(gr, true, true); in tu102_gr_init_fs()
52 tu102_gr_init_zcull(struct gf100_gr *gr) in tu102_gr_init_zcull() argument
54 struct nvkm_device *device = gr->base.engine.subdev.device; in tu102_gr_init_zcull()
55 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in tu102_gr_init_zcull()
56 const u8 tile_nr = ALIGN(gr->tpc_total, 64); in tu102_gr_init_zcull()
61 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in tu102_gr_init_zcull()
62 data |= bank[gr->tile[i + j]] << (j * 4); in tu102_gr_init_zcull()
63 bank[gr->tile[i + j]]++; in tu102_gr_init_zcull()
68 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in tu102_gr_init_zcull()
70 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in tu102_gr_init_zcull()
72 gr->tpc_total); in tu102_gr_init_zcull()
80 tu102_gr_init_gpc_mmu(struct gf100_gr *gr) in tu102_gr_init_gpc_mmu() argument
82 struct nvkm_device *device = gr->base.engine.subdev.device; in tu102_gr_init_gpc_mmu()