Lines Matching refs:hdr
26 wpr_header_dump(struct nvkm_subdev *subdev, const struct wpr_header *hdr) in wpr_header_dump() argument
29 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id); in wpr_header_dump()
30 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset); in wpr_header_dump()
31 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner); in wpr_header_dump()
32 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap); in wpr_header_dump()
33 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status); in wpr_header_dump()
37 wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr) in wpr_header_v1_dump() argument
40 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id); in wpr_header_v1_dump()
41 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset); in wpr_header_v1_dump()
42 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner); in wpr_header_v1_dump()
43 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap); in wpr_header_v1_dump()
44 nvkm_debug(subdev, "\tbinVersion : %d\n", hdr->bin_version); in wpr_header_v1_dump()
45 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status); in wpr_header_v1_dump()
49 lsb_header_tail_dump(struct nvkm_subdev *subdev, struct lsb_header_tail *hdr) in lsb_header_tail_dump() argument
52 nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off); in lsb_header_tail_dump()
53 nvkm_debug(subdev, "\tucodeSize : 0x%x\n", hdr->ucode_size); in lsb_header_tail_dump()
54 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); in lsb_header_tail_dump()
55 nvkm_debug(subdev, "\tblCodeSize : 0x%x\n", hdr->bl_code_size); in lsb_header_tail_dump()
56 nvkm_debug(subdev, "\tblImemOff : 0x%x\n", hdr->bl_imem_off); in lsb_header_tail_dump()
57 nvkm_debug(subdev, "\tblDataOff : 0x%x\n", hdr->bl_data_off); in lsb_header_tail_dump()
58 nvkm_debug(subdev, "\tblDataSize : 0x%x\n", hdr->bl_data_size); in lsb_header_tail_dump()
59 nvkm_debug(subdev, "\tappCodeOff : 0x%x\n", hdr->app_code_off); in lsb_header_tail_dump()
60 nvkm_debug(subdev, "\tappCodeSize : 0x%x\n", hdr->app_code_size); in lsb_header_tail_dump()
61 nvkm_debug(subdev, "\tappDataOff : 0x%x\n", hdr->app_data_off); in lsb_header_tail_dump()
62 nvkm_debug(subdev, "\tappDataSize : 0x%x\n", hdr->app_data_size); in lsb_header_tail_dump()
63 nvkm_debug(subdev, "\tflags : 0x%x\n", hdr->flags); in lsb_header_tail_dump()
67 lsb_header_dump(struct nvkm_subdev *subdev, struct lsb_header *hdr) in lsb_header_dump() argument
69 lsb_header_tail_dump(subdev, &hdr->tail); in lsb_header_dump()
73 lsb_header_v1_dump(struct nvkm_subdev *subdev, struct lsb_header_v1 *hdr) in lsb_header_v1_dump() argument
75 lsb_header_tail_dump(subdev, &hdr->tail); in lsb_header_v1_dump()
79 flcn_acr_desc_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc *hdr) in flcn_acr_desc_dump() argument
84 nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id); in flcn_acr_desc_dump()
85 nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset); in flcn_acr_desc_dump()
87 hdr->mmu_mem_range); in flcn_acr_desc_dump()
89 hdr->regions.no_regions); in flcn_acr_desc_dump()
91 for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) { in flcn_acr_desc_dump()
94 hdr->regions.region_props[i].start_addr); in flcn_acr_desc_dump()
96 hdr->regions.region_props[i].end_addr); in flcn_acr_desc_dump()
98 hdr->regions.region_props[i].region_id); in flcn_acr_desc_dump()
100 hdr->regions.region_props[i].read_mask); in flcn_acr_desc_dump()
102 hdr->regions.region_props[i].write_mask); in flcn_acr_desc_dump()
104 hdr->regions.region_props[i].client_mask); in flcn_acr_desc_dump()
108 hdr->ucode_blob_size); in flcn_acr_desc_dump()
110 hdr->ucode_blob_base); in flcn_acr_desc_dump()
112 hdr->vpr_desc.vpr_enabled); in flcn_acr_desc_dump()
114 hdr->vpr_desc.vpr_start); in flcn_acr_desc_dump()
116 hdr->vpr_desc.vpr_end); in flcn_acr_desc_dump()
118 hdr->vpr_desc.hdcp_policies); in flcn_acr_desc_dump()
122 flcn_acr_desc_v1_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc_v1 *hdr) in flcn_acr_desc_v1_dump() argument
127 nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id); in flcn_acr_desc_v1_dump()
128 nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset); in flcn_acr_desc_v1_dump()
130 hdr->mmu_memory_range); in flcn_acr_desc_v1_dump()
132 hdr->regions.no_regions); in flcn_acr_desc_v1_dump()
134 for (i = 0; i < ARRAY_SIZE(hdr->regions.region_props); i++) { in flcn_acr_desc_v1_dump()
137 hdr->regions.region_props[i].start_addr); in flcn_acr_desc_v1_dump()
139 hdr->regions.region_props[i].end_addr); in flcn_acr_desc_v1_dump()
141 hdr->regions.region_props[i].region_id); in flcn_acr_desc_v1_dump()
143 hdr->regions.region_props[i].read_mask); in flcn_acr_desc_v1_dump()
145 hdr->regions.region_props[i].write_mask); in flcn_acr_desc_v1_dump()
147 hdr->regions.region_props[i].client_mask); in flcn_acr_desc_v1_dump()
149 hdr->regions.region_props[i].shadow_mem_start_addr); in flcn_acr_desc_v1_dump()
153 hdr->ucode_blob_size); in flcn_acr_desc_v1_dump()
155 hdr->ucode_blob_base); in flcn_acr_desc_v1_dump()
157 hdr->vpr_desc.vpr_enabled); in flcn_acr_desc_v1_dump()
159 hdr->vpr_desc.vpr_start); in flcn_acr_desc_v1_dump()
161 hdr->vpr_desc.vpr_end); in flcn_acr_desc_v1_dump()
163 hdr->vpr_desc.hdcp_policies); in flcn_acr_desc_v1_dump()