Lines Matching refs:rdev
159 struct radeon_device *rdev = dev->dev_private; in radeon_is_px() local
161 if (rdev->flags & RADEON_IS_PX) in radeon_is_px()
166 static void radeon_device_handle_px_quirks(struct radeon_device *rdev) in radeon_device_handle_px_quirks() argument
172 if (rdev->pdev->vendor == p->chip_vendor && in radeon_device_handle_px_quirks()
173 rdev->pdev->device == p->chip_device && in radeon_device_handle_px_quirks()
174 rdev->pdev->subsystem_vendor == p->subsys_vendor && in radeon_device_handle_px_quirks()
175 rdev->pdev->subsystem_device == p->subsys_device) { in radeon_device_handle_px_quirks()
176 rdev->px_quirk_flags = p->px_quirk_flags; in radeon_device_handle_px_quirks()
182 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) in radeon_device_handle_px_quirks()
183 rdev->flags &= ~RADEON_IS_PX; in radeon_device_handle_px_quirks()
188 rdev->flags &= ~RADEON_IS_PX; in radeon_device_handle_px_quirks()
201 void radeon_program_register_sequence(struct radeon_device *rdev, in radeon_program_register_sequence() argument
227 void radeon_pci_config_reset(struct radeon_device *rdev) in radeon_pci_config_reset() argument
229 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); in radeon_pci_config_reset()
239 void radeon_surface_init(struct radeon_device *rdev) in radeon_surface_init() argument
242 if (rdev->family < CHIP_R600) { in radeon_surface_init()
246 if (rdev->surface_regs[i].bo) in radeon_surface_init()
247 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); in radeon_surface_init()
249 radeon_clear_surface_reg(rdev, i); in radeon_surface_init()
266 void radeon_scratch_init(struct radeon_device *rdev) in radeon_scratch_init() argument
271 if (rdev->family < CHIP_R300) { in radeon_scratch_init()
272 rdev->scratch.num_reg = 5; in radeon_scratch_init()
274 rdev->scratch.num_reg = 7; in radeon_scratch_init()
276 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; in radeon_scratch_init()
277 for (i = 0; i < rdev->scratch.num_reg; i++) { in radeon_scratch_init()
278 rdev->scratch.free[i] = true; in radeon_scratch_init()
279 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in radeon_scratch_init()
292 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) in radeon_scratch_get() argument
296 for (i = 0; i < rdev->scratch.num_reg; i++) { in radeon_scratch_get()
297 if (rdev->scratch.free[i]) { in radeon_scratch_get()
298 rdev->scratch.free[i] = false; in radeon_scratch_get()
299 *reg = rdev->scratch.reg[i]; in radeon_scratch_get()
314 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) in radeon_scratch_free() argument
318 for (i = 0; i < rdev->scratch.num_reg; i++) { in radeon_scratch_free()
319 if (rdev->scratch.reg[i] == reg) { in radeon_scratch_free()
320 rdev->scratch.free[i] = true; in radeon_scratch_free()
337 static int radeon_doorbell_init(struct radeon_device *rdev) in radeon_doorbell_init() argument
340 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); in radeon_doorbell_init()
341 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); in radeon_doorbell_init()
343 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); in radeon_doorbell_init()
344 if (rdev->doorbell.num_doorbells == 0) in radeon_doorbell_init()
347 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); in radeon_doorbell_init()
348 if (rdev->doorbell.ptr == NULL) { in radeon_doorbell_init()
351 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); in radeon_doorbell_init()
352 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); in radeon_doorbell_init()
354 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); in radeon_doorbell_init()
366 static void radeon_doorbell_fini(struct radeon_device *rdev) in radeon_doorbell_fini() argument
368 iounmap(rdev->doorbell.ptr); in radeon_doorbell_fini()
369 rdev->doorbell.ptr = NULL; in radeon_doorbell_fini()
381 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) in radeon_doorbell_get() argument
383 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); in radeon_doorbell_get()
384 if (offset < rdev->doorbell.num_doorbells) { in radeon_doorbell_get()
385 __set_bit(offset, rdev->doorbell.used); in radeon_doorbell_get()
401 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) in radeon_doorbell_free() argument
403 if (doorbell < rdev->doorbell.num_doorbells) in radeon_doorbell_free()
404 __clear_bit(doorbell, rdev->doorbell.used); in radeon_doorbell_free()
421 void radeon_wb_disable(struct radeon_device *rdev) in radeon_wb_disable() argument
423 rdev->wb.enabled = false; in radeon_wb_disable()
434 void radeon_wb_fini(struct radeon_device *rdev) in radeon_wb_fini() argument
436 radeon_wb_disable(rdev); in radeon_wb_fini()
437 if (rdev->wb.wb_obj) { in radeon_wb_fini()
438 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { in radeon_wb_fini()
439 radeon_bo_kunmap(rdev->wb.wb_obj); in radeon_wb_fini()
440 radeon_bo_unpin(rdev->wb.wb_obj); in radeon_wb_fini()
441 radeon_bo_unreserve(rdev->wb.wb_obj); in radeon_wb_fini()
443 radeon_bo_unref(&rdev->wb.wb_obj); in radeon_wb_fini()
444 rdev->wb.wb = NULL; in radeon_wb_fini()
445 rdev->wb.wb_obj = NULL; in radeon_wb_fini()
458 int radeon_wb_init(struct radeon_device *rdev) in radeon_wb_init() argument
462 if (rdev->wb.wb_obj == NULL) { in radeon_wb_init()
463 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, in radeon_wb_init()
465 &rdev->wb.wb_obj); in radeon_wb_init()
467 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); in radeon_wb_init()
470 r = radeon_bo_reserve(rdev->wb.wb_obj, false); in radeon_wb_init()
472 radeon_wb_fini(rdev); in radeon_wb_init()
475 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, in radeon_wb_init()
476 &rdev->wb.gpu_addr); in radeon_wb_init()
478 radeon_bo_unreserve(rdev->wb.wb_obj); in radeon_wb_init()
479 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); in radeon_wb_init()
480 radeon_wb_fini(rdev); in radeon_wb_init()
483 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); in radeon_wb_init()
484 radeon_bo_unreserve(rdev->wb.wb_obj); in radeon_wb_init()
486 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); in radeon_wb_init()
487 radeon_wb_fini(rdev); in radeon_wb_init()
493 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); in radeon_wb_init()
495 rdev->wb.use_event = false; in radeon_wb_init()
498 rdev->wb.enabled = false; in radeon_wb_init()
500 if (rdev->flags & RADEON_IS_AGP) { in radeon_wb_init()
502 rdev->wb.enabled = false; in radeon_wb_init()
503 } else if (rdev->family < CHIP_R300) { in radeon_wb_init()
505 rdev->wb.enabled = false; in radeon_wb_init()
507 rdev->wb.enabled = true; in radeon_wb_init()
509 if (rdev->family >= CHIP_R600) { in radeon_wb_init()
510 rdev->wb.use_event = true; in radeon_wb_init()
515 if (rdev->family >= CHIP_PALM) { in radeon_wb_init()
516 rdev->wb.enabled = true; in radeon_wb_init()
517 rdev->wb.use_event = true; in radeon_wb_init()
520 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); in radeon_wb_init()
566 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) in radeon_vram_location() argument
571 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { in radeon_vram_location()
572 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); in radeon_vram_location()
577 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { in radeon_vram_location()
578 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); in radeon_vram_location()
585 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", in radeon_vram_location()
602 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) in radeon_gtt_location() argument
606 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; in radeon_gtt_location()
610 dev_warn(rdev->dev, "limiting GTT\n"); in radeon_gtt_location()
616 dev_warn(rdev->dev, "limiting GTT\n"); in radeon_gtt_location()
622 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", in radeon_gtt_location()
655 bool radeon_card_posted(struct radeon_device *rdev) in radeon_card_posted() argument
660 if (rdev->family >= CHIP_BONAIRE && in radeon_card_posted()
666 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && in radeon_card_posted()
667 (rdev->family < CHIP_R600)) in radeon_card_posted()
670 if (ASIC_IS_NODCE(rdev)) in radeon_card_posted()
674 if (ASIC_IS_DCE4(rdev)) { in radeon_card_posted()
677 if (rdev->num_crtc >= 4) { in radeon_card_posted()
681 if (rdev->num_crtc >= 6) { in radeon_card_posted()
687 } else if (ASIC_IS_AVIVO(rdev)) { in radeon_card_posted()
703 if (rdev->family >= CHIP_R600) in radeon_card_posted()
723 void radeon_update_bandwidth_info(struct radeon_device *rdev) in radeon_update_bandwidth_info() argument
726 u32 sclk = rdev->pm.current_sclk; in radeon_update_bandwidth_info()
727 u32 mclk = rdev->pm.current_mclk; in radeon_update_bandwidth_info()
731 rdev->pm.sclk.full = dfixed_const(sclk); in radeon_update_bandwidth_info()
732 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); in radeon_update_bandwidth_info()
733 rdev->pm.mclk.full = dfixed_const(mclk); in radeon_update_bandwidth_info()
734 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); in radeon_update_bandwidth_info()
736 if (rdev->flags & RADEON_IS_IGP) { in radeon_update_bandwidth_info()
739 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); in radeon_update_bandwidth_info()
752 bool radeon_boot_test_post_card(struct radeon_device *rdev) in radeon_boot_test_post_card() argument
754 if (radeon_card_posted(rdev)) in radeon_boot_test_post_card()
757 if (rdev->bios) { in radeon_boot_test_post_card()
759 if (rdev->is_atom_bios) in radeon_boot_test_post_card()
760 atom_asic_init(rdev->mode_info.atom_context); in radeon_boot_test_post_card()
762 radeon_combios_asic_init(rdev->ddev); in radeon_boot_test_post_card()
765 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in radeon_boot_test_post_card()
780 int radeon_dummy_page_init(struct radeon_device *rdev) in radeon_dummy_page_init() argument
782 if (rdev->dummy_page.page) in radeon_dummy_page_init()
784 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); in radeon_dummy_page_init()
785 if (rdev->dummy_page.page == NULL) in radeon_dummy_page_init()
787 rdev->dummy_page.addr = dma_map_page(&rdev->pdev->dev, rdev->dummy_page.page, in radeon_dummy_page_init()
789 if (dma_mapping_error(&rdev->pdev->dev, rdev->dummy_page.addr)) { in radeon_dummy_page_init()
790 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); in radeon_dummy_page_init()
791 __free_page(rdev->dummy_page.page); in radeon_dummy_page_init()
792 rdev->dummy_page.page = NULL; in radeon_dummy_page_init()
795 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, in radeon_dummy_page_init()
807 void radeon_dummy_page_fini(struct radeon_device *rdev) in radeon_dummy_page_fini() argument
809 if (rdev->dummy_page.page == NULL) in radeon_dummy_page_fini()
811 dma_unmap_page(&rdev->pdev->dev, rdev->dummy_page.addr, PAGE_SIZE, in radeon_dummy_page_fini()
813 __free_page(rdev->dummy_page.page); in radeon_dummy_page_fini()
814 rdev->dummy_page.page = NULL; in radeon_dummy_page_fini()
838 struct radeon_device *rdev = info->dev->dev_private; in cail_pll_read() local
841 r = rdev->pll_rreg(rdev, reg); in cail_pll_read()
856 struct radeon_device *rdev = info->dev->dev_private; in cail_pll_write() local
858 rdev->pll_wreg(rdev, reg, val); in cail_pll_write()
872 struct radeon_device *rdev = info->dev->dev_private; in cail_mc_read() local
875 r = rdev->mc_rreg(rdev, reg); in cail_mc_read()
890 struct radeon_device *rdev = info->dev->dev_private; in cail_mc_write() local
892 rdev->mc_wreg(rdev, reg, val); in cail_mc_write()
906 struct radeon_device *rdev = info->dev->dev_private; in cail_reg_write() local
922 struct radeon_device *rdev = info->dev->dev_private; in cail_reg_read() local
940 struct radeon_device *rdev = info->dev->dev_private; in cail_ioreg_write() local
956 struct radeon_device *rdev = info->dev->dev_private; in cail_ioreg_read() local
973 int radeon_atombios_init(struct radeon_device *rdev) in radeon_atombios_init() argument
981 rdev->mode_info.atom_card_info = atom_card_info; in radeon_atombios_init()
982 atom_card_info->dev = rdev->ddev; in radeon_atombios_init()
986 if (rdev->rio_mem) { in radeon_atombios_init()
999 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); in radeon_atombios_init()
1000 if (!rdev->mode_info.atom_context) { in radeon_atombios_init()
1001 radeon_atombios_fini(rdev); in radeon_atombios_init()
1005 mutex_init(&rdev->mode_info.atom_context->mutex); in radeon_atombios_init()
1006 mutex_init(&rdev->mode_info.atom_context->scratch_mutex); in radeon_atombios_init()
1007 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); in radeon_atombios_init()
1008 atom_allocate_fb_scratch(rdev->mode_info.atom_context); in radeon_atombios_init()
1021 void radeon_atombios_fini(struct radeon_device *rdev) in radeon_atombios_fini() argument
1023 if (rdev->mode_info.atom_context) { in radeon_atombios_fini()
1024 kfree(rdev->mode_info.atom_context->scratch); in radeon_atombios_fini()
1026 kfree(rdev->mode_info.atom_context); in radeon_atombios_fini()
1027 rdev->mode_info.atom_context = NULL; in radeon_atombios_fini()
1028 kfree(rdev->mode_info.atom_card_info); in radeon_atombios_fini()
1029 rdev->mode_info.atom_card_info = NULL; in radeon_atombios_fini()
1048 int radeon_combios_init(struct radeon_device *rdev) in radeon_combios_init() argument
1050 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); in radeon_combios_init()
1062 void radeon_combios_fini(struct radeon_device *rdev) in radeon_combios_fini() argument
1079 struct radeon_device *rdev = dev->dev_private; in radeon_vga_set_decode() local
1080 radeon_vga_set_state(rdev, state); in radeon_vga_set_decode()
1126 static void radeon_check_arguments(struct radeon_device *rdev) in radeon_check_arguments() argument
1130 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", in radeon_check_arguments()
1136 radeon_gart_size = radeon_gart_size_auto(rdev->family); in radeon_check_arguments()
1140 dev_warn(rdev->dev, "gart size (%d) too small\n", in radeon_check_arguments()
1142 radeon_gart_size = radeon_gart_size_auto(rdev->family); in radeon_check_arguments()
1144 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", in radeon_check_arguments()
1146 radeon_gart_size = radeon_gart_size_auto(rdev->family); in radeon_check_arguments()
1148 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; in radeon_check_arguments()
1160 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " in radeon_check_arguments()
1167 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", in radeon_check_arguments()
1173 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n", in radeon_check_arguments()
1182 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", in radeon_check_arguments()
1203 dev_warn(rdev->dev, "VM page table size (%d) too small\n", in radeon_check_arguments()
1210 dev_warn(rdev->dev, "VM page table size (%d) too large\n", in radeon_check_arguments()
1289 int radeon_device_init(struct radeon_device *rdev, in radeon_device_init() argument
1298 rdev->shutdown = false; in radeon_device_init()
1299 rdev->dev = &pdev->dev; in radeon_device_init()
1300 rdev->ddev = ddev; in radeon_device_init()
1301 rdev->pdev = pdev; in radeon_device_init()
1302 rdev->flags = flags; in radeon_device_init()
1303 rdev->family = flags & RADEON_FAMILY_MASK; in radeon_device_init()
1304 rdev->is_atom_bios = false; in radeon_device_init()
1305 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; in radeon_device_init()
1306 rdev->mc.gtt_size = 512 * 1024 * 1024; in radeon_device_init()
1307 rdev->accel_working = false; in radeon_device_init()
1310 rdev->ring[i].idx = i; in radeon_device_init()
1312 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS); in radeon_device_init()
1315 radeon_family_name[rdev->family], pdev->vendor, pdev->device, in radeon_device_init()
1320 mutex_init(&rdev->ring_lock); in radeon_device_init()
1321 mutex_init(&rdev->dc_hw_i2c_mutex); in radeon_device_init()
1322 atomic_set(&rdev->ih.lock, 0); in radeon_device_init()
1323 mutex_init(&rdev->gem.mutex); in radeon_device_init()
1324 mutex_init(&rdev->pm.mutex); in radeon_device_init()
1325 mutex_init(&rdev->gpu_clock_mutex); in radeon_device_init()
1326 mutex_init(&rdev->srbm_mutex); in radeon_device_init()
1327 init_rwsem(&rdev->pm.mclk_lock); in radeon_device_init()
1328 init_rwsem(&rdev->exclusive_lock); in radeon_device_init()
1329 init_waitqueue_head(&rdev->irq.vblank_queue); in radeon_device_init()
1330 r = radeon_gem_init(rdev); in radeon_device_init()
1334 radeon_check_arguments(rdev); in radeon_device_init()
1338 rdev->vm_manager.max_pfn = radeon_vm_size << 18; in radeon_device_init()
1341 r = radeon_asic_init(rdev); in radeon_device_init()
1348 if ((rdev->family >= CHIP_RS400) && in radeon_device_init()
1349 (rdev->flags & RADEON_IS_IGP)) { in radeon_device_init()
1350 rdev->flags &= ~RADEON_IS_AGP; in radeon_device_init()
1353 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { in radeon_device_init()
1354 radeon_agp_disable(rdev); in radeon_device_init()
1361 if (rdev->family >= CHIP_CAYMAN) in radeon_device_init()
1362 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ in radeon_device_init()
1363 else if (rdev->family >= CHIP_CEDAR) in radeon_device_init()
1364 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ in radeon_device_init()
1366 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ in radeon_device_init()
1375 if (rdev->flags & RADEON_IS_AGP) in radeon_device_init()
1377 if ((rdev->flags & RADEON_IS_PCI) && in radeon_device_init()
1378 (rdev->family <= CHIP_RS740)) in radeon_device_init()
1381 if (rdev->family == CHIP_CEDAR) in radeon_device_init()
1385 r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits)); in radeon_device_init()
1390 rdev->need_swiotlb = drm_need_swiotlb(dma_bits); in radeon_device_init()
1394 spin_lock_init(&rdev->mmio_idx_lock); in radeon_device_init()
1395 spin_lock_init(&rdev->smc_idx_lock); in radeon_device_init()
1396 spin_lock_init(&rdev->pll_idx_lock); in radeon_device_init()
1397 spin_lock_init(&rdev->mc_idx_lock); in radeon_device_init()
1398 spin_lock_init(&rdev->pcie_idx_lock); in radeon_device_init()
1399 spin_lock_init(&rdev->pciep_idx_lock); in radeon_device_init()
1400 spin_lock_init(&rdev->pif_idx_lock); in radeon_device_init()
1401 spin_lock_init(&rdev->cg_idx_lock); in radeon_device_init()
1402 spin_lock_init(&rdev->uvd_idx_lock); in radeon_device_init()
1403 spin_lock_init(&rdev->rcu_idx_lock); in radeon_device_init()
1404 spin_lock_init(&rdev->didt_idx_lock); in radeon_device_init()
1405 spin_lock_init(&rdev->end_idx_lock); in radeon_device_init()
1406 if (rdev->family >= CHIP_BONAIRE) { in radeon_device_init()
1407 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); in radeon_device_init()
1408 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); in radeon_device_init()
1410 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); in radeon_device_init()
1411 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); in radeon_device_init()
1413 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); in radeon_device_init()
1414 if (rdev->rmmio == NULL) in radeon_device_init()
1418 if (rdev->family >= CHIP_BONAIRE) in radeon_device_init()
1419 radeon_doorbell_init(rdev); in radeon_device_init()
1423 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { in radeon_device_init()
1424 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); in radeon_device_init()
1425 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); in radeon_device_init()
1429 if (rdev->rio_mem == NULL) in radeon_device_init()
1432 if (rdev->flags & RADEON_IS_PX) in radeon_device_init()
1433 radeon_device_handle_px_quirks(rdev); in radeon_device_init()
1438 vga_client_register(rdev->pdev, radeon_vga_set_decode); in radeon_device_init()
1440 if (rdev->flags & RADEON_IS_PX) in radeon_device_init()
1442 if (!pci_is_thunderbolt_attached(rdev->pdev)) in radeon_device_init()
1443 vga_switcheroo_register_client(rdev->pdev, in radeon_device_init()
1446 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); in radeon_device_init()
1448 r = radeon_init(rdev); in radeon_device_init()
1452 radeon_gem_debugfs_init(rdev); in radeon_device_init()
1453 radeon_mst_debugfs_init(rdev); in radeon_device_init()
1455 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { in radeon_device_init()
1459 radeon_asic_reset(rdev); in radeon_device_init()
1460 radeon_fini(rdev); in radeon_device_init()
1461 radeon_agp_disable(rdev); in radeon_device_init()
1462 r = radeon_init(rdev); in radeon_device_init()
1467 r = radeon_ib_ring_tests(rdev); in radeon_device_init()
1476 if (rdev->pm.dpm_enabled && in radeon_device_init()
1477 (rdev->pm.pm_method == PM_METHOD_DPM) && in radeon_device_init()
1478 (rdev->family == CHIP_TURKS) && in radeon_device_init()
1479 (rdev->flags & RADEON_IS_MOBILITY)) { in radeon_device_init()
1480 mutex_lock(&rdev->pm.mutex); in radeon_device_init()
1481 radeon_dpm_disable(rdev); in radeon_device_init()
1482 radeon_dpm_enable(rdev); in radeon_device_init()
1483 mutex_unlock(&rdev->pm.mutex); in radeon_device_init()
1487 if (rdev->accel_working) in radeon_device_init()
1488 radeon_test_moves(rdev); in radeon_device_init()
1493 if (rdev->accel_working) in radeon_device_init()
1494 radeon_test_syncing(rdev); in radeon_device_init()
1499 if (rdev->accel_working) in radeon_device_init()
1500 radeon_benchmark(rdev, radeon_benchmarking); in radeon_device_init()
1511 vga_switcheroo_fini_domain_pm_ops(rdev->dev); in radeon_device_init()
1523 void radeon_device_fini(struct radeon_device *rdev) in radeon_device_fini() argument
1526 rdev->shutdown = true; in radeon_device_fini()
1528 radeon_bo_evict_vram(rdev); in radeon_device_fini()
1529 radeon_fini(rdev); in radeon_device_fini()
1530 if (!pci_is_thunderbolt_attached(rdev->pdev)) in radeon_device_fini()
1531 vga_switcheroo_unregister_client(rdev->pdev); in radeon_device_fini()
1532 if (rdev->flags & RADEON_IS_PX) in radeon_device_fini()
1533 vga_switcheroo_fini_domain_pm_ops(rdev->dev); in radeon_device_fini()
1534 vga_client_unregister(rdev->pdev); in radeon_device_fini()
1535 if (rdev->rio_mem) in radeon_device_fini()
1536 pci_iounmap(rdev->pdev, rdev->rio_mem); in radeon_device_fini()
1537 rdev->rio_mem = NULL; in radeon_device_fini()
1538 iounmap(rdev->rmmio); in radeon_device_fini()
1539 rdev->rmmio = NULL; in radeon_device_fini()
1540 if (rdev->family >= CHIP_BONAIRE) in radeon_device_fini()
1541 radeon_doorbell_fini(rdev); in radeon_device_fini()
1558 struct radeon_device *rdev; in radeon_suspend_kms() local
1568 rdev = dev->dev_private; in radeon_suspend_kms()
1603 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { in radeon_suspend_kms()
1612 radeon_bo_evict_vram(rdev); in radeon_suspend_kms()
1616 r = radeon_fence_wait_empty(rdev, i); in radeon_suspend_kms()
1619 radeon_fence_driver_force_completion(rdev, i); in radeon_suspend_kms()
1623 radeon_save_bios_scratch_regs(rdev); in radeon_suspend_kms()
1625 radeon_suspend(rdev); in radeon_suspend_kms()
1626 radeon_hpd_fini(rdev); in radeon_suspend_kms()
1631 radeon_bo_evict_vram(rdev); in radeon_suspend_kms()
1633 radeon_agp_suspend(rdev); in radeon_suspend_kms()
1636 if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) { in radeon_suspend_kms()
1637 rdev->asic->asic_reset(rdev, true); in radeon_suspend_kms()
1647 radeon_fbdev_set_suspend(rdev, 1); in radeon_suspend_kms()
1663 struct radeon_device *rdev = dev->dev_private; in radeon_resume_kms() local
1684 radeon_agp_resume(rdev); in radeon_resume_kms()
1685 radeon_resume(rdev); in radeon_resume_kms()
1687 r = radeon_ib_ring_tests(rdev); in radeon_resume_kms()
1691 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in radeon_resume_kms()
1693 r = radeon_pm_late_init(rdev); in radeon_resume_kms()
1695 rdev->pm.dpm_enabled = false; in radeon_resume_kms()
1700 radeon_pm_resume(rdev); in radeon_resume_kms()
1703 radeon_restore_bios_scratch_regs(rdev); in radeon_resume_kms()
1716 ASIC_IS_AVIVO(rdev) ? in radeon_resume_kms()
1727 if (rdev->is_atom_bios) { in radeon_resume_kms()
1728 radeon_atom_encoder_init(rdev); in radeon_resume_kms()
1729 radeon_atom_disp_eng_pll_init(rdev); in radeon_resume_kms()
1731 if (rdev->mode_info.bl_encoder) { in radeon_resume_kms()
1732 u8 bl_level = radeon_get_backlight_level(rdev, in radeon_resume_kms()
1733 rdev->mode_info.bl_encoder); in radeon_resume_kms()
1734 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, in radeon_resume_kms()
1739 radeon_hpd_init(rdev); in radeon_resume_kms()
1754 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) in radeon_resume_kms()
1755 radeon_pm_compute_clocks(rdev); in radeon_resume_kms()
1758 radeon_fbdev_set_suspend(rdev, 0); in radeon_resume_kms()
1773 int radeon_gpu_reset(struct radeon_device *rdev) in radeon_gpu_reset() argument
1783 down_write(&rdev->exclusive_lock); in radeon_gpu_reset()
1785 if (!rdev->needs_reset) { in radeon_gpu_reset()
1786 up_write(&rdev->exclusive_lock); in radeon_gpu_reset()
1790 atomic_inc(&rdev->gpu_reset_counter); in radeon_gpu_reset()
1792 radeon_save_bios_scratch_regs(rdev); in radeon_gpu_reset()
1794 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); in radeon_gpu_reset()
1795 radeon_suspend(rdev); in radeon_gpu_reset()
1796 radeon_hpd_fini(rdev); in radeon_gpu_reset()
1799 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], in radeon_gpu_reset()
1803 dev_info(rdev->dev, "Saved %d dwords of commands " in radeon_gpu_reset()
1808 r = radeon_asic_reset(rdev); in radeon_gpu_reset()
1810 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); in radeon_gpu_reset()
1811 radeon_resume(rdev); in radeon_gpu_reset()
1814 radeon_restore_bios_scratch_regs(rdev); in radeon_gpu_reset()
1818 radeon_ring_restore(rdev, &rdev->ring[i], in radeon_gpu_reset()
1821 radeon_fence_driver_force_completion(rdev, i); in radeon_gpu_reset()
1826 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in radeon_gpu_reset()
1828 r = radeon_pm_late_init(rdev); in radeon_gpu_reset()
1830 rdev->pm.dpm_enabled = false; in radeon_gpu_reset()
1835 radeon_pm_resume(rdev); in radeon_gpu_reset()
1839 if (rdev->is_atom_bios) { in radeon_gpu_reset()
1840 radeon_atom_encoder_init(rdev); in radeon_gpu_reset()
1841 radeon_atom_disp_eng_pll_init(rdev); in radeon_gpu_reset()
1843 if (rdev->mode_info.bl_encoder) { in radeon_gpu_reset()
1844 u8 bl_level = radeon_get_backlight_level(rdev, in radeon_gpu_reset()
1845 rdev->mode_info.bl_encoder); in radeon_gpu_reset()
1846 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, in radeon_gpu_reset()
1851 radeon_hpd_init(rdev); in radeon_gpu_reset()
1853 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); in radeon_gpu_reset()
1855 rdev->in_reset = true; in radeon_gpu_reset()
1856 rdev->needs_reset = false; in radeon_gpu_reset()
1858 downgrade_write(&rdev->exclusive_lock); in radeon_gpu_reset()
1860 drm_helper_resume_force_mode(rdev->ddev); in radeon_gpu_reset()
1863 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) in radeon_gpu_reset()
1864 radeon_pm_compute_clocks(rdev); in radeon_gpu_reset()
1867 r = radeon_ib_ring_tests(rdev); in radeon_gpu_reset()
1872 dev_info(rdev->dev, "GPU reset failed\n"); in radeon_gpu_reset()
1875 rdev->needs_reset = r == -EAGAIN; in radeon_gpu_reset()
1876 rdev->in_reset = false; in radeon_gpu_reset()
1878 up_read(&rdev->exclusive_lock); in radeon_gpu_reset()