Lines Matching refs:pcr
16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr) in rts5249_get_ic_version() argument
20 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); in rts5249_get_ic_version()
24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage) in rts5249_fill_driving() argument
42 drive_sel = pcr->sd30_drive_sel_3v3; in rts5249_fill_driving()
45 drive_sel = pcr->sd30_drive_sel_1v8; in rts5249_fill_driving()
48 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, in rts5249_fill_driving()
50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, in rts5249_fill_driving()
52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, in rts5249_fill_driving()
56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) in rtsx_base_fetch_vendor_settings() argument
58 struct pci_dev *pdev = pcr->pci; in rtsx_base_fetch_vendor_settings()
62 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); in rtsx_base_fetch_vendor_settings()
65 pcr_dbg(pcr, "skip fetch vendor setting\n"); in rtsx_base_fetch_vendor_settings()
69 pcr->aspm_en = rtsx_reg_to_aspm(reg); in rtsx_base_fetch_vendor_settings()
70 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); in rtsx_base_fetch_vendor_settings()
71 pcr->card_drive_sel &= 0x3F; in rtsx_base_fetch_vendor_settings()
72 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); in rtsx_base_fetch_vendor_settings()
75 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); in rtsx_base_fetch_vendor_settings()
77 pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg); in rtsx_base_fetch_vendor_settings()
80 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rtsx_base_fetch_vendor_settings()
81 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); in rtsx_base_fetch_vendor_settings()
83 pcr->flags |= PCR_REVERSE_SOCKET; in rtsx_base_fetch_vendor_settings()
86 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) in rts5249_init_from_cfg() argument
88 struct pci_dev *pdev = pcr->pci; in rts5249_init_from_cfg()
90 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_from_cfg()
99 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_init_from_cfg()
101 rtsx_pci_enable_oobs_polling(pcr); in rts5249_init_from_cfg()
103 rtsx_pci_disable_oobs_polling(pcr); in rts5249_init_from_cfg()
108 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); in rts5249_init_from_cfg()
111 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); in rts5249_init_from_cfg()
114 rtsx_set_dev_flag(pcr, PM_L1_1_EN); in rts5249_init_from_cfg()
117 rtsx_set_dev_flag(pcr, PM_L1_2_EN); in rts5249_init_from_cfg()
126 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); in rts5249_init_from_cfg()
133 static int rts5249_init_from_hw(struct rtsx_pcr *pcr) in rts5249_init_from_hw() argument
135 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_from_hw()
137 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN in rts5249_init_from_hw()
146 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr) in rts52xa_save_content_from_efuse() argument
154 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_from_efuse()
158 pcr_dbg(pcr, "Enable efuse por!"); in rts52xa_save_content_from_efuse()
159 pcr_dbg(pcr, "save efuse to autoload"); in rts52xa_save_content_from_efuse()
161 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00); in rts52xa_save_content_from_efuse()
162 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
166 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
170 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
176 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
178 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
182 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
186 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
187 rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val); in rts52xa_save_content_from_efuse()
190 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); in rts52xa_save_content_from_efuse()
191 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); in rts52xa_save_content_from_efuse()
192 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); in rts52xa_save_content_from_efuse()
193 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); in rts52xa_save_content_from_efuse()
198 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
201 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
203 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
207 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
211 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
212 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val); in rts52xa_save_content_from_efuse()
214 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80); in rts52xa_save_content_from_efuse()
215 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_from_efuse()
217 pcr_dbg(pcr, "Disable efuse por!"); in rts52xa_save_content_from_efuse()
220 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr) in rts52xa_save_content_to_autoload_space() argument
224 rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val); in rts52xa_save_content_to_autoload_space()
226 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val); in rts52xa_save_content_to_autoload_space()
228 rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG, in rts52xa_save_content_to_autoload_space()
231 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_to_autoload_space()
234 pcr_dbg(pcr, "Power ON efuse!"); in rts52xa_save_content_to_autoload_space()
236 rts52xa_save_content_from_efuse(pcr); in rts52xa_save_content_to_autoload_space()
238 rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val); in rts52xa_save_content_to_autoload_space()
240 rts52xa_save_content_from_efuse(pcr); in rts52xa_save_content_to_autoload_space()
243 pcr_dbg(pcr, "Load from autoload"); in rts52xa_save_content_to_autoload_space()
244 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80); in rts52xa_save_content_to_autoload_space()
245 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); in rts52xa_save_content_to_autoload_space()
246 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); in rts52xa_save_content_to_autoload_space()
247 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); in rts52xa_save_content_to_autoload_space()
248 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); in rts52xa_save_content_to_autoload_space()
252 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) in rts5249_extra_init_hw() argument
254 struct rtsx_cr_option *option = &(pcr->option); in rts5249_extra_init_hw()
256 rts5249_init_from_cfg(pcr); in rts5249_extra_init_hw()
257 rts5249_init_from_hw(pcr); in rts5249_extra_init_hw()
259 rtsx_pci_init_cmd(pcr); in rts5249_extra_init_hw()
261 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) in rts5249_extra_init_hw()
262 rts52xa_save_content_to_autoload_space(pcr); in rts5249_extra_init_hw()
265 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); in rts5249_extra_init_hw()
267 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); in rts5249_extra_init_hw()
269 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); in rts5249_extra_init_hw()
271 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); in rts5249_extra_init_hw()
272 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); in rts5249_extra_init_hw()
274 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); in rts5249_extra_init_hw()
276 rts5249_fill_driving(pcr, OUTPUT_3V3); in rts5249_extra_init_hw()
277 if (pcr->flags & PCR_REVERSE_SOCKET) in rts5249_extra_init_hw()
278 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); in rts5249_extra_init_hw()
280 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); in rts5249_extra_init_hw()
282 rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); in rts5249_extra_init_hw()
284 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) in rts5249_extra_init_hw()
285 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN); in rts5249_extra_init_hw()
287 if (pcr->rtd3_en) { in rts5249_extra_init_hw()
288 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
289 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01); in rts5249_extra_init_hw()
290 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30); in rts5249_extra_init_hw()
292 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01); in rts5249_extra_init_hw()
293 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33); in rts5249_extra_init_hw()
296 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
297 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00); in rts5249_extra_init_hw()
298 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20); in rts5249_extra_init_hw()
300 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30); in rts5249_extra_init_hw()
301 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00); in rts5249_extra_init_hw()
311 rtsx_pci_write_register(pcr, PETXCFG, in rts5249_extra_init_hw()
314 rtsx_pci_write_register(pcr, PETXCFG, in rts5249_extra_init_hw()
317 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); in rts5249_extra_init_hw()
318 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
319 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts5249_extra_init_hw()
321 pcr_dbg(pcr, "Power OFF efuse!"); in rts5249_extra_init_hw()
327 static int rts5249_optimize_phy(struct rtsx_pcr *pcr) in rts5249_optimize_phy() argument
331 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00); in rts5249_optimize_phy()
335 err = rtsx_pci_write_phy_register(pcr, PHY_REV, in rts5249_optimize_phy()
346 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, in rts5249_optimize_phy()
352 err = rtsx_pci_write_phy_register(pcr, PHY_PCR, in rts5249_optimize_phy()
359 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, in rts5249_optimize_phy()
366 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, in rts5249_optimize_phy()
373 err = rtsx_pci_write_phy_register(pcr, PHY_RDR, in rts5249_optimize_phy()
377 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, in rts5249_optimize_phy()
381 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, in rts5249_optimize_phy()
387 return rtsx_pci_write_phy_register(pcr, PHY_TUNE, in rts5249_optimize_phy()
393 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr) in rtsx_base_turn_on_led() argument
395 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); in rtsx_base_turn_on_led()
398 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr) in rtsx_base_turn_off_led() argument
400 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); in rtsx_base_turn_off_led()
403 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr) in rtsx_base_enable_auto_blink() argument
405 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); in rtsx_base_enable_auto_blink()
408 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr) in rtsx_base_disable_auto_blink() argument
410 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); in rtsx_base_disable_auto_blink()
413 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card) in rtsx_base_card_power_on() argument
416 struct rtsx_cr_option *option = &pcr->option; in rtsx_base_card_power_on()
419 rtsx_pci_enable_ocp(pcr); in rtsx_base_card_power_on()
421 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_on()
422 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_on()
424 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_on()
426 err = rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_on()
432 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_on()
433 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_on()
435 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_on()
437 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_on()
440 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card) in rtsx_base_card_power_off() argument
442 struct rtsx_cr_option *option = &pcr->option; in rtsx_base_card_power_off()
445 rtsx_pci_disable_ocp(pcr); in rtsx_base_card_power_off()
447 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF); in rtsx_base_card_power_off()
449 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00); in rtsx_base_card_power_off()
453 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rtsx_base_switch_output_voltage() argument
460 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, in rtsx_base_switch_output_voltage()
467 if (CHK_PCI_PID(pcr, 0x5249)) { in rtsx_base_switch_output_voltage()
468 err = rtsx_pci_update_phy(pcr, PHY_BACR, in rtsx_base_switch_output_voltage()
475 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, in rtsx_base_switch_output_voltage()
481 pcr_dbg(pcr, "unknown output voltage %d\n", voltage); in rtsx_base_switch_output_voltage()
486 rtsx_pci_init_cmd(pcr); in rtsx_base_switch_output_voltage()
487 rts5249_fill_driving(pcr, voltage); in rtsx_base_switch_output_voltage()
488 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_switch_output_voltage()
556 void rts5249_init_params(struct rtsx_pcr *pcr) in rts5249_init_params() argument
558 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_params()
560 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; in rts5249_init_params()
561 pcr->num_slots = 2; in rts5249_init_params()
562 pcr->ops = &rts5249_pcr_ops; in rts5249_init_params()
564 pcr->flags = 0; in rts5249_init_params()
565 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; in rts5249_init_params()
566 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; in rts5249_init_params()
567 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; in rts5249_init_params()
568 pcr->aspm_en = ASPM_L1_EN; in rts5249_init_params()
569 pcr->aspm_mode = ASPM_MODE_CFG; in rts5249_init_params()
570 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); in rts5249_init_params()
571 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); in rts5249_init_params()
573 pcr->ic_version = rts5249_get_ic_version(pcr); in rts5249_init_params()
574 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl; in rts5249_init_params()
575 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl; in rts5249_init_params()
576 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl; in rts5249_init_params()
577 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl; in rts5249_init_params()
579 pcr->reg_pm_ctrl3 = PM_CTRL3; in rts5249_init_params()
595 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) in rts524a_write_phy() argument
599 return __rtsx_pci_write_phy_register(pcr, addr, val); in rts524a_write_phy()
602 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) in rts524a_read_phy() argument
606 return __rtsx_pci_read_phy_register(pcr, addr, val); in rts524a_read_phy()
609 static int rts524a_optimize_phy(struct rtsx_pcr *pcr) in rts524a_optimize_phy() argument
613 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts524a_optimize_phy()
618 rtsx_pci_write_phy_register(pcr, PHY_PCR, in rts524a_optimize_phy()
621 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, in rts524a_optimize_phy()
624 if (is_version(pcr, 0x524A, IC_VER_A)) { in rts524a_optimize_phy()
625 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, in rts524a_optimize_phy()
627 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, in rts524a_optimize_phy()
630 rtsx_pci_write_phy_register(pcr, PHY_ANA1A, in rts524a_optimize_phy()
633 rtsx_pci_write_phy_register(pcr, PHY_ANA1D, in rts524a_optimize_phy()
635 rtsx_pci_write_phy_register(pcr, PHY_DIG1E, in rts524a_optimize_phy()
645 rtsx_pci_write_phy_register(pcr, PHY_ANA08, in rts524a_optimize_phy()
652 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr) in rts524a_extra_init_hw() argument
654 rts5249_extra_init_hw(pcr); in rts524a_extra_init_hw()
656 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, in rts524a_extra_init_hw()
658 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); in rts524a_extra_init_hw()
659 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN, in rts524a_extra_init_hw()
661 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); in rts524a_extra_init_hw()
662 if (is_version(pcr, 0x524A, IC_VER_A)) { in rts524a_extra_init_hw()
663 rtsx_pci_write_register(pcr, LDO_DV18_CFG, in rts524a_extra_init_hw()
665 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, in rts524a_extra_init_hw()
667 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts524a_extra_init_hw()
669 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts524a_extra_init_hw()
671 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, in rts524a_extra_init_hw()
673 rtsx_pci_write_register(pcr, SD40_LDO_CTL1, in rts524a_extra_init_hw()
680 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) in rts5250_set_l1off_cfg_sub_d0() argument
682 struct rtsx_cr_option *option = &(pcr->option); in rts5250_set_l1off_cfg_sub_d0()
684 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); in rts5250_set_l1off_cfg_sub_d0()
689 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); in rts5250_set_l1off_cfg_sub_d0()
690 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); in rts5250_set_l1off_cfg_sub_d0()
703 if (rtsx_check_dev_flag(pcr, in rts5250_set_l1off_cfg_sub_d0()
711 rtsx_set_l1off_sub(pcr, val); in rts5250_set_l1off_cfg_sub_d0()
730 void rts524a_init_params(struct rtsx_pcr *pcr) in rts524a_init_params() argument
732 rts5249_init_params(pcr); in rts524a_init_params()
733 pcr->aspm_mode = ASPM_MODE_REG; in rts524a_init_params()
734 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); in rts524a_init_params()
735 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; in rts524a_init_params()
736 pcr->option.ltr_l1off_snooze_sspwrgate = in rts524a_init_params()
739 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; in rts524a_init_params()
740 pcr->ops = &rts524a_pcr_ops; in rts524a_init_params()
742 pcr->option.ocp_en = 1; in rts524a_init_params()
743 if (pcr->option.ocp_en) in rts524a_init_params()
744 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; in rts524a_init_params()
745 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; in rts524a_init_params()
746 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800; in rts524a_init_params()
750 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card) in rts525a_card_power_on() argument
752 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, in rts525a_card_power_on()
754 return rtsx_base_card_power_on(pcr, card); in rts525a_card_power_on()
757 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rts525a_switch_output_voltage() argument
761 rtsx_pci_write_register(pcr, LDO_CONFIG2, in rts525a_switch_output_voltage()
763 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); in rts525a_switch_output_voltage()
766 rtsx_pci_write_register(pcr, LDO_CONFIG2, in rts525a_switch_output_voltage()
768 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, in rts525a_switch_output_voltage()
775 rtsx_pci_init_cmd(pcr); in rts525a_switch_output_voltage()
776 rts5249_fill_driving(pcr, voltage); in rts525a_switch_output_voltage()
777 return rtsx_pci_send_cmd(pcr, 100); in rts525a_switch_output_voltage()
780 static int rts525a_optimize_phy(struct rtsx_pcr *pcr) in rts525a_optimize_phy() argument
784 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts525a_optimize_phy()
789 rtsx_pci_write_phy_register(pcr, _PHY_FLD0, in rts525a_optimize_phy()
794 rtsx_pci_write_phy_register(pcr, _PHY_ANA03, in rts525a_optimize_phy()
798 if (is_version(pcr, 0x525A, IC_VER_A)) in rts525a_optimize_phy()
799 rtsx_pci_write_phy_register(pcr, _PHY_REV0, in rts525a_optimize_phy()
806 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr) in rts525a_extra_init_hw() argument
808 rts5249_extra_init_hw(pcr); in rts525a_extra_init_hw()
810 rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD); in rts525a_extra_init_hw()
812 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); in rts525a_extra_init_hw()
813 if (is_version(pcr, 0x525A, IC_VER_A)) { in rts525a_extra_init_hw()
814 rtsx_pci_write_register(pcr, L1SUB_CONFIG2, in rts525a_extra_init_hw()
816 rtsx_pci_write_register(pcr, RREF_CFG, in rts525a_extra_init_hw()
818 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts525a_extra_init_hw()
820 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, in rts525a_extra_init_hw()
822 rtsx_pci_write_register(pcr, LDO_AV12S_CFG, in rts525a_extra_init_hw()
824 rtsx_pci_write_register(pcr, LDO_VCC_CFG0, in rts525a_extra_init_hw()
826 rtsx_pci_write_register(pcr, OOBS_CONFIG, in rts525a_extra_init_hw()
847 void rts525a_init_params(struct rtsx_pcr *pcr) in rts525a_init_params() argument
849 rts5249_init_params(pcr); in rts525a_init_params()
850 pcr->aspm_mode = ASPM_MODE_REG; in rts525a_init_params()
851 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11); in rts525a_init_params()
852 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; in rts525a_init_params()
853 pcr->option.ltr_l1off_snooze_sspwrgate = in rts525a_init_params()
856 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; in rts525a_init_params()
857 pcr->ops = &rts525a_pcr_ops; in rts525a_init_params()
859 pcr->option.ocp_en = 1; in rts525a_init_params()
860 if (pcr->option.ocp_en) in rts525a_init_params()
861 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; in rts525a_init_params()
862 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; in rts525a_init_params()
863 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800; in rts525a_init_params()