Lines Matching refs:pcr
18 static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr) in rts5261_get_ic_version() argument
22 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); in rts5261_get_ic_version()
26 static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage) in rts5261_fill_driving() argument
44 drive_sel = pcr->sd30_drive_sel_3v3; in rts5261_fill_driving()
47 drive_sel = pcr->sd30_drive_sel_1v8; in rts5261_fill_driving()
50 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL, in rts5261_fill_driving()
53 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL, in rts5261_fill_driving()
56 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL, in rts5261_fill_driving()
60 static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr) in rtsx5261_fetch_vendor_settings() argument
62 struct pci_dev *pdev = pcr->pci; in rtsx5261_fetch_vendor_settings()
67 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); in rtsx5261_fetch_vendor_settings()
71 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rtsx5261_fetch_vendor_settings()
72 pcr_dbg(pcr, "skip fetch vendor setting\n"); in rtsx5261_fetch_vendor_settings()
77 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rtsx5261_fetch_vendor_settings()
80 pcr->rtd3_en = rts5261_reg_to_rtd3(reg); in rtsx5261_fetch_vendor_settings()
83 pcr->flags |= PCR_REVERSE_SOCKET; in rtsx5261_fetch_vendor_settings()
87 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); in rtsx5261_fetch_vendor_settings()
89 pcr->aspm_en = rts5261_reg_to_aspm(reg); in rtsx5261_fetch_vendor_settings()
90 pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg); in rtsx5261_fetch_vendor_settings()
91 pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg); in rtsx5261_fetch_vendor_settings()
94 static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) in rts5261_force_power_down() argument
97 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); in rts5261_force_power_down()
98 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); in rts5261_force_power_down()
99 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, in rts5261_force_power_down()
103 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, in rts5261_force_power_down()
106 rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL, in rts5261_force_power_down()
110 static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr) in rts5261_enable_auto_blink() argument
112 return rtsx_pci_write_register(pcr, OLT_LED_CTL, in rts5261_enable_auto_blink()
116 static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr) in rts5261_disable_auto_blink() argument
118 return rtsx_pci_write_register(pcr, OLT_LED_CTL, in rts5261_disable_auto_blink()
122 static int rts5261_turn_on_led(struct rtsx_pcr *pcr) in rts5261_turn_on_led() argument
124 return rtsx_pci_write_register(pcr, GPIO_CTL, in rts5261_turn_on_led()
128 static int rts5261_turn_off_led(struct rtsx_pcr *pcr) in rts5261_turn_off_led() argument
130 return rtsx_pci_write_register(pcr, GPIO_CTL, in rts5261_turn_off_led()
160 static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr) in rts5261_sd_set_sample_push_timing_sd30() argument
162 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK in rts5261_sd_set_sample_push_timing_sd30()
164 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in rts5261_sd_set_sample_push_timing_sd30()
165 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF, in rts5261_sd_set_sample_push_timing_sd30()
167 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5261_sd_set_sample_push_timing_sd30()
172 static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card) in rts5261_card_power_on() argument
174 struct rtsx_cr_option *option = &pcr->option; in rts5261_card_power_on()
177 rtsx_pci_enable_ocp(pcr); in rts5261_card_power_on()
179 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, in rts5261_card_power_on()
182 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1, in rts5261_card_power_on()
184 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL, in rts5261_card_power_on()
187 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL, in rts5261_card_power_on()
192 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); in rts5261_card_power_on()
195 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF, in rts5261_card_power_on()
198 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL, in rts5261_card_power_on()
200 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0); in rts5261_card_power_on()
201 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR, in rts5261_card_power_on()
205 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0); in rts5261_card_power_on()
206 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG, in rts5261_card_power_on()
210 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 || in rts5261_card_power_on()
211 pcr->extra_caps & EXTRA_CAPS_SD_SDR104) in rts5261_card_power_on()
212 rts5261_sd_set_sample_push_timing_sd30(pcr); in rts5261_card_power_on()
217 static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rts5261_switch_output_voltage() argument
222 rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL, in rts5261_switch_output_voltage()
227 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val); in rts5261_switch_output_voltage()
229 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); in rts5261_switch_output_voltage()
233 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG, in rts5261_switch_output_voltage()
235 rtsx_pci_write_register(pcr, SD_PAD_CTL, in rts5261_switch_output_voltage()
239 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val); in rts5261_switch_output_voltage()
241 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); in rts5261_switch_output_voltage()
245 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG, in rts5261_switch_output_voltage()
247 rtsx_pci_write_register(pcr, SD_PAD_CTL, in rts5261_switch_output_voltage()
255 rts5261_fill_driving(pcr, voltage); in rts5261_switch_output_voltage()
260 static void rts5261_stop_cmd(struct rtsx_pcr *pcr) in rts5261_stop_cmd() argument
262 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); in rts5261_stop_cmd()
263 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); in rts5261_stop_cmd()
264 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0, in rts5261_stop_cmd()
267 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH); in rts5261_stop_cmd()
270 static void rts5261_card_before_power_off(struct rtsx_pcr *pcr) in rts5261_card_before_power_off() argument
272 rts5261_stop_cmd(pcr); in rts5261_card_before_power_off()
273 rts5261_switch_output_voltage(pcr, OUTPUT_3V3); in rts5261_card_before_power_off()
277 static void rts5261_enable_ocp(struct rtsx_pcr *pcr) in rts5261_enable_ocp() argument
282 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_enable_ocp()
285 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); in rts5261_enable_ocp()
289 static void rts5261_disable_ocp(struct rtsx_pcr *pcr) in rts5261_disable_ocp() argument
294 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rts5261_disable_ocp()
295 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_disable_ocp()
300 static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card) in rts5261_card_power_off() argument
304 rts5261_card_before_power_off(pcr); in rts5261_card_power_off()
305 err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL, in rts5261_card_power_off()
308 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, in rts5261_card_power_off()
310 if (pcr->option.ocp_en) in rts5261_card_power_off()
311 rtsx_pci_disable_ocp(pcr); in rts5261_card_power_off()
316 static void rts5261_init_ocp(struct rtsx_pcr *pcr) in rts5261_init_ocp() argument
318 struct rtsx_cr_option *option = &pcr->option; in rts5261_init_ocp()
323 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_init_ocp()
327 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_init_ocp()
330 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_init_ocp()
335 val = pcr->hw_param.ocp_glitch; in rts5261_init_ocp()
336 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val); in rts5261_init_ocp()
338 rts5261_enable_ocp(pcr); in rts5261_init_ocp()
340 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_init_ocp()
345 static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr) in rts5261_clear_ocpstat() argument
353 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); in rts5261_clear_ocpstat()
356 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rts5261_clear_ocpstat()
360 static void rts5261_process_ocp(struct rtsx_pcr *pcr) in rts5261_process_ocp() argument
362 if (!pcr->option.ocp_en) in rts5261_process_ocp()
365 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); in rts5261_process_ocp()
367 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { in rts5261_process_ocp()
368 rts5261_clear_ocpstat(pcr); in rts5261_process_ocp()
369 rts5261_card_power_off(pcr, RTSX_SD_CARD); in rts5261_process_ocp()
370 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); in rts5261_process_ocp()
371 pcr->ocp_stat = 0; in rts5261_process_ocp()
376 static int rts5261_init_from_hw(struct rtsx_pcr *pcr) in rts5261_init_from_hw() argument
378 struct pci_dev *pdev = pcr->pci; in rts5261_init_from_hw()
383 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_init_from_hw()
387 rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR, in rts5261_init_from_hw()
389 rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL, in rts5261_init_from_hw()
395 rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp); in rts5261_init_from_hw()
399 rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp); in rts5261_init_from_hw()
401 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid); in rts5261_init_from_hw()
406 pcr_dbg(pcr, "read 0x814 DW fail\n"); in rts5261_init_from_hw()
407 pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval); in rts5261_init_from_hw()
410 pcr_dbg(pcr, "0x816: %d\n", valid); in rts5261_init_from_hw()
412 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_init_from_hw()
414 pcr_dbg(pcr, "Disable efuse por!\n"); in rts5261_init_from_hw()
420 pcr_dbg(pcr, "write config fail\n"); in rts5261_init_from_hw()
425 static void rts5261_init_from_cfg(struct rtsx_pcr *pcr) in rts5261_init_from_cfg() argument
427 struct pci_dev *pdev = pcr->pci; in rts5261_init_from_cfg()
430 struct rtsx_cr_option *option = &pcr->option; in rts5261_init_from_cfg()
439 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); in rts5261_init_from_cfg()
441 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); in rts5261_init_from_cfg()
444 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); in rts5261_init_from_cfg()
446 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); in rts5261_init_from_cfg()
449 rtsx_set_dev_flag(pcr, PM_L1_1_EN); in rts5261_init_from_cfg()
451 rtsx_clear_dev_flag(pcr, PM_L1_1_EN); in rts5261_init_from_cfg()
454 rtsx_set_dev_flag(pcr, PM_L1_2_EN); in rts5261_init_from_cfg()
456 rtsx_clear_dev_flag(pcr, PM_L1_2_EN); in rts5261_init_from_cfg()
458 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); in rts5261_init_from_cfg()
466 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); in rts5261_init_from_cfg()
472 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN in rts5261_init_from_cfg()
479 static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) in rts5261_extra_init_hw() argument
481 struct rtsx_cr_option *option = &pcr->option; in rts5261_extra_init_hw()
484 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1, in rts5261_extra_init_hw()
487 rts5261_init_from_cfg(pcr); in rts5261_extra_init_hw()
488 rts5261_init_from_hw(pcr); in rts5261_extra_init_hw()
491 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_extra_init_hw()
493 rtsx_pci_write_register(pcr, L1SUB_CONFIG1, in rts5261_extra_init_hw()
495 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0); in rts5261_extra_init_hw()
497 if (is_version_higher_than(pcr, PID_5261, IC_VER_B)) { in rts5261_extra_init_hw()
498 val = rtsx_pci_readl(pcr, RTSX_DUM_REG); in rts5261_extra_init_hw()
499 rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1); in rts5261_extra_init_hw()
501 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4, in rts5261_extra_init_hw()
505 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4, in rts5261_extra_init_hw()
507 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, in rts5261_extra_init_hw()
510 rtsx_pci_write_register(pcr, PCLK_CTL, in rts5261_extra_init_hw()
513 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); in rts5261_extra_init_hw()
514 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN); in rts5261_extra_init_hw()
517 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02); in rts5261_extra_init_hw()
520 rts5261_fill_driving(pcr, OUTPUT_3V3); in rts5261_extra_init_hw()
522 if (pcr->flags & PCR_REVERSE_SOCKET) in rts5261_extra_init_hw()
523 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30); in rts5261_extra_init_hw()
525 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); in rts5261_extra_init_hw()
532 rtsx_pci_write_register(pcr, PETXCFG, in rts5261_extra_init_hw()
535 rtsx_pci_write_register(pcr, PETXCFG, in rts5261_extra_init_hw()
538 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); in rts5261_extra_init_hw()
539 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); in rts5261_extra_init_hw()
540 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_extra_init_hw()
544 rtsx_pci_write_register(pcr, RTS5261_FW_CTL, in rts5261_extra_init_hw()
550 static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable) in rts5261_enable_aspm() argument
555 if (pcr->aspm_enabled == enable) in rts5261_enable_aspm()
558 val |= (pcr->aspm_en & 0x02); in rts5261_enable_aspm()
559 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); in rts5261_enable_aspm()
560 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rts5261_enable_aspm()
561 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en); in rts5261_enable_aspm()
562 pcr->aspm_enabled = enable; in rts5261_enable_aspm()
565 static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable) in rts5261_disable_aspm() argument
570 if (pcr->aspm_enabled == enable) in rts5261_disable_aspm()
573 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rts5261_disable_aspm()
575 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); in rts5261_disable_aspm()
576 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); in rts5261_disable_aspm()
578 pcr->aspm_enabled = enable; in rts5261_disable_aspm()
581 static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable) in rts5261_set_aspm() argument
584 rts5261_enable_aspm(pcr, true); in rts5261_set_aspm()
586 rts5261_disable_aspm(pcr, false); in rts5261_set_aspm()
589 static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) in rts5261_set_l1off_cfg_sub_d0() argument
591 struct rtsx_cr_option *option = &pcr->option; in rts5261_set_l1off_cfg_sub_d0()
595 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); in rts5261_set_l1off_cfg_sub_d0()
596 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); in rts5261_set_l1off_cfg_sub_d0()
608 rtsx_set_l1off_sub(pcr, val); in rts5261_set_l1off_cfg_sub_d0()
637 int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, in rts5261_pci_switch_clock() argument
652 if (is_version_higher_than(pcr, PID_5261, IC_VER_C)) { in rts5261_pci_switch_clock()
662 err = rtsx_pci_write_register(pcr, SD_CFG1, in rts5261_pci_switch_clock()
668 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); in rts5261_pci_switch_clock()
673 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", in rts5261_pci_switch_clock()
674 clk, pcr->cur_clock); in rts5261_pci_switch_clock()
676 if (clk == pcr->cur_clock) in rts5261_pci_switch_clock()
679 if (pcr->ops->conv_clk_and_div_n) in rts5261_pci_switch_clock()
680 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); in rts5261_pci_switch_clock()
692 if (pcr->ops->conv_clk_and_div_n) { in rts5261_pci_switch_clock()
693 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, in rts5261_pci_switch_clock()
695 n = pcr->ops->conv_clk_and_div_n(dbl_clk, in rts5261_pci_switch_clock()
704 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); in rts5261_pci_switch_clock()
730 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); in rts5261_pci_switch_clock()
732 rtsx_pci_init_cmd(pcr); in rts5261_pci_switch_clock()
733 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in rts5261_pci_switch_clock()
735 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rts5261_pci_switch_clock()
737 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in rts5261_pci_switch_clock()
738 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, in rts5261_pci_switch_clock()
740 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); in rts5261_pci_switch_clock()
741 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); in rts5261_pci_switch_clock()
743 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rts5261_pci_switch_clock()
745 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, in rts5261_pci_switch_clock()
747 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rts5261_pci_switch_clock()
749 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, in rts5261_pci_switch_clock()
753 err = rtsx_pci_send_cmd(pcr, 2000); in rts5261_pci_switch_clock()
759 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5261_pci_switch_clock()
763 pcr->cur_clock = clk; in rts5261_pci_switch_clock()
768 void rts5261_init_params(struct rtsx_pcr *pcr) in rts5261_init_params() argument
770 struct rtsx_cr_option *option = &pcr->option; in rts5261_init_params()
771 struct rtsx_hw_param *hw_param = &pcr->hw_param; in rts5261_init_params()
774 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; in rts5261_init_params()
775 rtsx_pci_read_register(pcr, RTS5261_FW_STATUS, &val); in rts5261_init_params()
777 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS; in rts5261_init_params()
778 pcr->num_slots = 1; in rts5261_init_params()
779 pcr->ops = &rts5261_pcr_ops; in rts5261_init_params()
781 pcr->flags = 0; in rts5261_init_params()
782 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; in rts5261_init_params()
783 pcr->sd30_drive_sel_1v8 = 0x00; in rts5261_init_params()
784 pcr->sd30_drive_sel_3v3 = 0x00; in rts5261_init_params()
785 pcr->aspm_en = ASPM_L1_EN; in rts5261_init_params()
786 pcr->aspm_mode = ASPM_MODE_REG; in rts5261_init_params()
787 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11); in rts5261_init_params()
788 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); in rts5261_init_params()
790 pcr->ic_version = rts5261_get_ic_version(pcr); in rts5261_init_params()
791 pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl; in rts5261_init_params()
792 pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl; in rts5261_init_params()
794 pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3; in rts5261_init_params()