Lines Matching refs:dev
58 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) in mei_me_mecbrw_read() argument
60 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); in mei_me_mecbrw_read()
69 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) in mei_me_hcbww_write() argument
71 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); in mei_me_hcbww_write()
81 static inline u32 mei_me_mecsr_read(const struct mei_device *dev) in mei_me_mecsr_read() argument
85 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); in mei_me_mecsr_read()
86 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); in mei_me_mecsr_read()
98 static inline u32 mei_hcsr_read(const struct mei_device *dev) in mei_hcsr_read() argument
102 reg = mei_me_reg_read(to_me_hw(dev), H_CSR); in mei_hcsr_read()
103 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_read()
114 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) in mei_hcsr_write() argument
116 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_write()
117 mei_me_reg_write(to_me_hw(dev), H_CSR, reg); in mei_hcsr_write()
127 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) in mei_hcsr_set() argument
130 mei_hcsr_write(dev, reg); in mei_hcsr_set()
138 static inline void mei_hcsr_set_hig(struct mei_device *dev) in mei_hcsr_set_hig() argument
142 hcsr = mei_hcsr_read(dev) | H_IG; in mei_hcsr_set_hig()
143 mei_hcsr_set(dev, hcsr); in mei_hcsr_set_hig()
153 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev) in mei_me_d0i3c_read() argument
157 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); in mei_me_d0i3c_read()
158 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_read()
169 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) in mei_me_d0i3c_write() argument
171 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_write()
172 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); in mei_me_d0i3c_write()
183 static int mei_me_trc_status(struct mei_device *dev, u32 *trc) in mei_me_trc_status() argument
185 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_trc_status()
191 trace_mei_reg_read(dev->dev, "ME_TRC", ME_TRC, *trc); in mei_me_trc_status()
204 static int mei_me_fw_status(struct mei_device *dev, in mei_me_fw_status() argument
207 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_fw_status()
217 ret = hw->read_fws(dev, fw_src->status[i], in mei_me_fw_status()
219 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_X", in mei_me_fw_status()
239 static int mei_me_hw_config(struct mei_device *dev) in mei_me_hw_config() argument
241 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_config()
248 hcsr = mei_hcsr_read(dev); in mei_me_hw_config()
252 hw->read_fws(dev, PCI_CFG_HFS_1, ®); in mei_me_hw_config()
253 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); in mei_me_hw_config()
259 reg = mei_me_d0i3c_read(dev); in mei_me_hw_config()
275 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) in mei_me_pg_state() argument
277 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_state()
294 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr) in me_intr_disable() argument
297 mei_hcsr_set(dev, hcsr); in me_intr_disable()
306 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr) in me_intr_clear() argument
309 mei_hcsr_write(dev, hcsr); in me_intr_clear()
317 static void mei_me_intr_clear(struct mei_device *dev) in mei_me_intr_clear() argument
319 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_clear()
321 me_intr_clear(dev, hcsr); in mei_me_intr_clear()
328 static void mei_me_intr_enable(struct mei_device *dev) in mei_me_intr_enable() argument
330 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_enable()
333 mei_hcsr_set(dev, hcsr); in mei_me_intr_enable()
341 static void mei_me_intr_disable(struct mei_device *dev) in mei_me_intr_disable() argument
343 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_disable()
345 me_intr_disable(dev, hcsr); in mei_me_intr_disable()
353 static void mei_me_synchronize_irq(struct mei_device *dev) in mei_me_synchronize_irq() argument
355 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_synchronize_irq()
365 static void mei_me_hw_reset_release(struct mei_device *dev) in mei_me_hw_reset_release() argument
367 u32 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset_release()
371 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset_release()
379 static void mei_me_host_set_ready(struct mei_device *dev) in mei_me_host_set_ready() argument
381 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_set_ready()
384 mei_hcsr_set(dev, hcsr); in mei_me_host_set_ready()
393 static bool mei_me_host_is_ready(struct mei_device *dev) in mei_me_host_is_ready() argument
395 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_is_ready()
406 static bool mei_me_hw_is_ready(struct mei_device *dev) in mei_me_hw_is_ready() argument
408 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_ready()
419 static bool mei_me_hw_is_resetting(struct mei_device *dev) in mei_me_hw_is_resetting() argument
421 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_resetting()
433 static int mei_me_hw_ready_wait(struct mei_device *dev) in mei_me_hw_ready_wait() argument
435 mutex_unlock(&dev->device_lock); in mei_me_hw_ready_wait()
436 wait_event_timeout(dev->wait_hw_ready, in mei_me_hw_ready_wait()
437 dev->recvd_hw_ready, in mei_me_hw_ready_wait()
439 mutex_lock(&dev->device_lock); in mei_me_hw_ready_wait()
440 if (!dev->recvd_hw_ready) { in mei_me_hw_ready_wait()
441 dev_err(dev->dev, "wait hw ready failed\n"); in mei_me_hw_ready_wait()
445 mei_me_hw_reset_release(dev); in mei_me_hw_ready_wait()
446 dev->recvd_hw_ready = false; in mei_me_hw_ready_wait()
456 static int mei_me_hw_start(struct mei_device *dev) in mei_me_hw_start() argument
458 int ret = mei_me_hw_ready_wait(dev); in mei_me_hw_start()
462 dev_dbg(dev->dev, "hw is ready\n"); in mei_me_hw_start()
464 mei_me_host_set_ready(dev); in mei_me_hw_start()
476 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) in mei_hbuf_filled_slots() argument
481 hcsr = mei_hcsr_read(dev); in mei_hbuf_filled_slots()
496 static bool mei_me_hbuf_is_empty(struct mei_device *dev) in mei_me_hbuf_is_empty() argument
498 return mei_hbuf_filled_slots(dev) == 0; in mei_me_hbuf_is_empty()
508 static int mei_me_hbuf_empty_slots(struct mei_device *dev) in mei_me_hbuf_empty_slots() argument
510 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hbuf_empty_slots()
513 filled_slots = mei_hbuf_filled_slots(dev); in mei_me_hbuf_empty_slots()
530 static u32 mei_me_hbuf_depth(const struct mei_device *dev) in mei_me_hbuf_depth() argument
532 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hbuf_depth()
548 static int mei_me_hbuf_write(struct mei_device *dev, in mei_me_hbuf_write() argument
561 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); in mei_me_hbuf_write()
563 empty_slots = mei_hbuf_empty_slots(dev); in mei_me_hbuf_write()
564 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); in mei_me_hbuf_write()
575 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_hbuf_write()
579 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_hbuf_write()
586 mei_me_hcbww_write(dev, reg); in mei_me_hbuf_write()
589 mei_hcsr_set_hig(dev); in mei_me_hbuf_write()
590 if (!mei_me_hw_is_ready(dev)) in mei_me_hbuf_write()
603 static int mei_me_count_full_read_slots(struct mei_device *dev) in mei_me_count_full_read_slots() argument
609 me_csr = mei_me_mecsr_read(dev); in mei_me_count_full_read_slots()
619 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); in mei_me_count_full_read_slots()
632 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, in mei_me_read_slots() argument
638 *reg_buf++ = mei_me_mecbrw_read(dev); in mei_me_read_slots()
641 u32 reg = mei_me_mecbrw_read(dev); in mei_me_read_slots()
646 mei_hcsr_set_hig(dev); in mei_me_read_slots()
655 static void mei_me_pg_set(struct mei_device *dev) in mei_me_pg_set() argument
657 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_set()
661 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
665 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
674 static void mei_me_pg_unset(struct mei_device *dev) in mei_me_pg_unset() argument
676 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_unset()
680 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
686 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
697 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) in mei_me_pg_legacy_enter_sync() argument
699 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_enter_sync()
703 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_enter_sync()
705 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_pg_legacy_enter_sync()
709 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
710 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_enter_sync()
711 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); in mei_me_pg_legacy_enter_sync()
712 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
714 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_enter_sync()
715 mei_me_pg_set(dev); in mei_me_pg_legacy_enter_sync()
721 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_enter_sync()
734 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) in mei_me_pg_legacy_exit_sync() argument
736 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_exit_sync()
740 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) in mei_me_pg_legacy_exit_sync()
743 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_exit_sync()
745 mei_me_pg_unset(dev); in mei_me_pg_legacy_exit_sync()
747 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
748 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
749 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); in mei_me_pg_legacy_exit_sync()
750 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
753 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_exit_sync()
758 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_legacy_exit_sync()
759 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); in mei_me_pg_legacy_exit_sync()
763 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
764 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
765 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); in mei_me_pg_legacy_exit_sync()
766 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
768 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED) in mei_me_pg_legacy_exit_sync()
774 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_exit_sync()
787 static bool mei_me_pg_in_transition(struct mei_device *dev) in mei_me_pg_in_transition() argument
789 return dev->pg_event >= MEI_PG_EVENT_WAIT && in mei_me_pg_in_transition()
790 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_in_transition()
800 static bool mei_me_pg_is_enabled(struct mei_device *dev) in mei_me_pg_is_enabled() argument
802 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_is_enabled()
803 u32 reg = mei_me_mecsr_read(dev); in mei_me_pg_is_enabled()
811 if (!dev->hbm_f_pg_supported) in mei_me_pg_is_enabled()
817 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n", in mei_me_pg_is_enabled()
820 dev->version.major_version, in mei_me_pg_is_enabled()
821 dev->version.minor_version, in mei_me_pg_is_enabled()
836 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr) in mei_me_d0i3_set() argument
838 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
845 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_set()
847 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
858 static u32 mei_me_d0i3_unset(struct mei_device *dev) in mei_me_d0i3_unset() argument
860 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
864 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_unset()
866 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
877 static int mei_me_d0i3_enter_sync(struct mei_device *dev) in mei_me_d0i3_enter_sync() argument
879 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter_sync()
885 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
888 dev_dbg(dev->dev, "d0i3 set not needed\n"); in mei_me_d0i3_enter_sync()
894 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_d0i3_enter_sync()
896 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_d0i3_enter_sync()
901 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
902 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
903 dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout); in mei_me_d0i3_enter_sync()
904 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
906 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_d0i3_enter_sync()
912 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_enter_sync()
914 reg = mei_me_d0i3_set(dev, true); in mei_me_d0i3_enter_sync()
916 dev_dbg(dev->dev, "d0i3 enter wait not needed\n"); in mei_me_d0i3_enter_sync()
921 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
922 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
923 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout); in mei_me_d0i3_enter_sync()
924 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
926 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_enter_sync()
927 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
938 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter_sync()
939 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret); in mei_me_d0i3_enter_sync()
953 static int mei_me_d0i3_enter(struct mei_device *dev) in mei_me_d0i3_enter() argument
955 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter()
958 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter()
961 dev_dbg(dev->dev, "already d0i3 : set not needed\n"); in mei_me_d0i3_enter()
965 mei_me_d0i3_set(dev, false); in mei_me_d0i3_enter()
968 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter()
969 dev_dbg(dev->dev, "d0i3 enter\n"); in mei_me_d0i3_enter()
980 static int mei_me_d0i3_exit_sync(struct mei_device *dev) in mei_me_d0i3_exit_sync() argument
982 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_exit_sync()
987 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_exit_sync()
989 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
992 dev_dbg(dev->dev, "d0i3 exit not needed\n"); in mei_me_d0i3_exit_sync()
997 reg = mei_me_d0i3_unset(dev); in mei_me_d0i3_exit_sync()
999 dev_dbg(dev->dev, "d0i3 exit wait not needed\n"); in mei_me_d0i3_exit_sync()
1004 mutex_unlock(&dev->device_lock); in mei_me_d0i3_exit_sync()
1005 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_exit_sync()
1006 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); in mei_me_d0i3_exit_sync()
1007 mutex_lock(&dev->device_lock); in mei_me_d0i3_exit_sync()
1009 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_exit_sync()
1010 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
1021 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_exit_sync()
1023 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret); in mei_me_d0i3_exit_sync()
1033 static void mei_me_pg_legacy_intr(struct mei_device *dev) in mei_me_pg_legacy_intr() argument
1035 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_intr()
1037 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT) in mei_me_pg_legacy_intr()
1040 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_pg_legacy_intr()
1042 if (waitqueue_active(&dev->wait_pg)) in mei_me_pg_legacy_intr()
1043 wake_up(&dev->wait_pg); in mei_me_pg_legacy_intr()
1052 static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source) in mei_me_d0i3_intr() argument
1054 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_intr()
1056 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT && in mei_me_d0i3_intr()
1058 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_d0i3_intr()
1061 if (dev->hbm_state != MEI_HBM_IDLE) { in mei_me_d0i3_intr()
1066 dev_dbg(dev->dev, "d0i3 set host ready\n"); in mei_me_d0i3_intr()
1067 mei_me_host_set_ready(dev); in mei_me_d0i3_intr()
1073 wake_up(&dev->wait_pg); in mei_me_d0i3_intr()
1082 dev_dbg(dev->dev, "d0i3 want resume\n"); in mei_me_d0i3_intr()
1083 mei_hbm_pg_resume(dev); in mei_me_d0i3_intr()
1093 static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source) in mei_me_pg_intr() argument
1095 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_intr()
1098 mei_me_d0i3_intr(dev, intr_source); in mei_me_pg_intr()
1100 mei_me_pg_legacy_intr(dev); in mei_me_pg_intr()
1110 int mei_me_pg_enter_sync(struct mei_device *dev) in mei_me_pg_enter_sync() argument
1112 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_enter_sync()
1115 return mei_me_d0i3_enter_sync(dev); in mei_me_pg_enter_sync()
1117 return mei_me_pg_legacy_enter_sync(dev); in mei_me_pg_enter_sync()
1127 int mei_me_pg_exit_sync(struct mei_device *dev) in mei_me_pg_exit_sync() argument
1129 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_exit_sync()
1132 return mei_me_d0i3_exit_sync(dev); in mei_me_pg_exit_sync()
1134 return mei_me_pg_legacy_exit_sync(dev); in mei_me_pg_exit_sync()
1145 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) in mei_me_hw_reset() argument
1147 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_reset()
1152 mei_me_intr_enable(dev); in mei_me_hw_reset()
1154 ret = mei_me_d0i3_exit_sync(dev); in mei_me_hw_reset()
1160 pm_runtime_set_active(dev->dev); in mei_me_hw_reset()
1162 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1169 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); in mei_me_hw_reset()
1171 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset()
1172 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1180 dev->recvd_hw_ready = false; in mei_me_hw_reset()
1181 mei_hcsr_write(dev, hcsr); in mei_me_hw_reset()
1187 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1190 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); in mei_me_hw_reset()
1193 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); in mei_me_hw_reset()
1196 mei_me_hw_reset_release(dev); in mei_me_hw_reset()
1198 ret = mei_me_d0i3_enter(dev); in mei_me_hw_reset()
1216 struct mei_device *dev = (struct mei_device *)dev_id; in mei_me_irq_quick_handler() local
1219 hcsr = mei_hcsr_read(dev); in mei_me_irq_quick_handler()
1223 dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr)); in mei_me_irq_quick_handler()
1226 me_intr_disable(dev, hcsr); in mei_me_irq_quick_handler()
1242 struct mei_device *dev = (struct mei_device *) dev_id; in mei_me_irq_thread_handler() local
1248 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); in mei_me_irq_thread_handler()
1250 mutex_lock(&dev->device_lock); in mei_me_irq_thread_handler()
1252 hcsr = mei_hcsr_read(dev); in mei_me_irq_thread_handler()
1253 me_intr_clear(dev, hcsr); in mei_me_irq_thread_handler()
1258 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { in mei_me_irq_thread_handler()
1259 dev_warn(dev->dev, "FW not ready: resetting.\n"); in mei_me_irq_thread_handler()
1260 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1264 if (mei_me_hw_is_resetting(dev)) in mei_me_irq_thread_handler()
1265 mei_hcsr_set_hig(dev); in mei_me_irq_thread_handler()
1267 mei_me_pg_intr(dev, me_intr_src(hcsr)); in mei_me_irq_thread_handler()
1270 if (!mei_host_is_ready(dev)) { in mei_me_irq_thread_handler()
1271 if (mei_hw_is_ready(dev)) { in mei_me_irq_thread_handler()
1272 dev_dbg(dev->dev, "we need to start the dev.\n"); in mei_me_irq_thread_handler()
1273 dev->recvd_hw_ready = true; in mei_me_irq_thread_handler()
1274 wake_up(&dev->wait_hw_ready); in mei_me_irq_thread_handler()
1276 dev_dbg(dev->dev, "Spurious Interrupt\n"); in mei_me_irq_thread_handler()
1281 slots = mei_count_full_read_slots(dev); in mei_me_irq_thread_handler()
1283 dev_dbg(dev->dev, "slots to read = %08x\n", slots); in mei_me_irq_thread_handler()
1284 rets = mei_irq_read_handler(dev, &cmpl_list, &slots); in mei_me_irq_thread_handler()
1293 (dev->dev_state != MEI_DEV_RESETTING && in mei_me_irq_thread_handler()
1294 dev->dev_state != MEI_DEV_POWER_DOWN)) { in mei_me_irq_thread_handler()
1295 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", in mei_me_irq_thread_handler()
1297 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1302 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1309 if (dev->pg_event != MEI_PG_EVENT_WAIT && in mei_me_irq_thread_handler()
1310 dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_irq_thread_handler()
1311 rets = mei_irq_write_handler(dev, &cmpl_list); in mei_me_irq_thread_handler()
1312 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1315 mei_irq_compl_handler(dev, &cmpl_list); in mei_me_irq_thread_handler()
1318 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); in mei_me_irq_thread_handler()
1319 mei_me_intr_enable(dev); in mei_me_irq_thread_handler()
1320 mutex_unlock(&dev->device_lock); in mei_me_irq_thread_handler()
1374 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg); in mei_me_fw_type_nm()
1400 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); in mei_me_fw_type_sps_4()
1425 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg); in mei_me_fw_type_sps()
1428 dev_dbg(&pdev->dev, "fw type is %d\n", fw_type); in mei_me_fw_type_sps()
1611 struct mei_device *dev; in mei_me_dev_init() local
1615 dev = devm_kzalloc(parent, sizeof(*dev) + sizeof(*hw), GFP_KERNEL); in mei_me_dev_init()
1616 if (!dev) in mei_me_dev_init()
1619 hw = to_me_hw(dev); in mei_me_dev_init()
1622 dev->dr_dscr[i].size = cfg->dma_size[i]; in mei_me_dev_init()
1624 mei_device_init(dev, parent, &mei_me_hw_ops); in mei_me_dev_init()
1627 dev->fw_f_fw_ver_supported = cfg->fw_ver_supported; in mei_me_dev_init()
1629 dev->kind = cfg->kind; in mei_me_dev_init()
1631 return dev; in mei_me_dev_init()