Lines Matching refs:ret_val
28 s32 ret_val; in igb_get_bus_info_pcie() local
34 ret_val = igb_read_pcie_cap_reg(hw, in igb_get_bus_info_pcie()
37 if (ret_val) { in igb_get_bus_info_pcie()
290 s32 ret_val = 0; in igb_check_alt_mac_addr() local
300 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, in igb_check_alt_mac_addr()
302 if (ret_val) { in igb_check_alt_mac_addr()
321 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); in igb_check_alt_mac_addr()
322 if (ret_val) { in igb_check_alt_mac_addr()
344 return ret_val; in igb_check_alt_mac_addr()
610 s32 ret_val; in igb_check_for_copper_link() local
619 ret_val = 0; in igb_check_for_copper_link()
627 ret_val = igb_phy_has_link(hw, 1, 0, &link); in igb_check_for_copper_link()
628 if (ret_val) in igb_check_for_copper_link()
645 ret_val = -E1000_ERR_CONFIG; in igb_check_for_copper_link()
660 ret_val = igb_config_fc_after_link_up(hw); in igb_check_for_copper_link()
661 if (ret_val) in igb_check_for_copper_link()
665 return ret_val; in igb_check_for_copper_link()
680 s32 ret_val = 0; in igb_setup_link() local
692 ret_val = igb_set_default_fc(hw); in igb_setup_link()
693 if (ret_val) in igb_setup_link()
706 ret_val = hw->mac.ops.setup_physical_interface(hw); in igb_setup_link()
707 if (ret_val) in igb_setup_link()
726 return ret_val; in igb_setup_link()
792 s32 ret_val = 0; in igb_set_default_fc() local
809 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG + lan_offset, in igb_set_default_fc()
811 if (ret_val) { in igb_set_default_fc()
824 return ret_val; in igb_set_default_fc()
840 s32 ret_val = 0; in igb_force_mac_fc() local
880 ret_val = -E1000_ERR_CONFIG; in igb_force_mac_fc()
887 return ret_val; in igb_force_mac_fc()
903 s32 ret_val = 0; in igb_config_fc_after_link_up() local
914 ret_val = igb_force_mac_fc(hw); in igb_config_fc_after_link_up()
917 ret_val = igb_force_mac_fc(hw); in igb_config_fc_after_link_up()
920 if (ret_val) { in igb_config_fc_after_link_up()
935 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igb_config_fc_after_link_up()
937 if (ret_val) in igb_config_fc_after_link_up()
939 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igb_config_fc_after_link_up()
941 if (ret_val) in igb_config_fc_after_link_up()
955 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, in igb_config_fc_after_link_up()
957 if (ret_val) in igb_config_fc_after_link_up()
959 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, in igb_config_fc_after_link_up()
961 if (ret_val) in igb_config_fc_after_link_up()
1075 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); in igb_config_fc_after_link_up()
1076 if (ret_val) { in igb_config_fc_after_link_up()
1087 ret_val = igb_force_mac_fc(hw); in igb_config_fc_after_link_up()
1088 if (ret_val) { in igb_config_fc_after_link_up()
1107 return ret_val; in igb_config_fc_after_link_up()
1210 ret_val = igb_force_mac_fc(hw); in igb_config_fc_after_link_up()
1211 if (ret_val) { in igb_config_fc_after_link_up()
1213 return ret_val; in igb_config_fc_after_link_up()
1218 return ret_val; in igb_config_fc_after_link_up()
1267 s32 ret_val = 0; in igb_get_hw_semaphore() local
1283 ret_val = -E1000_ERR_NVM; in igb_get_hw_semaphore()
1303 ret_val = -E1000_ERR_NVM; in igb_get_hw_semaphore()
1308 return ret_val; in igb_get_hw_semaphore()
1337 s32 ret_val = 0; in igb_get_auto_rd_done() local
1349 ret_val = -E1000_ERR_RESET; in igb_get_auto_rd_done()
1354 return ret_val; in igb_get_auto_rd_done()
1367 s32 ret_val; in igb_valid_led_default() local
1369 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); in igb_valid_led_default()
1370 if (ret_val) { in igb_valid_led_default()
1387 return ret_val; in igb_valid_led_default()
1398 s32 ret_val; in igb_id_led_init() local
1408 ret_val = igb_valid_led_default_i210(hw, &data); in igb_id_led_init()
1410 ret_val = igb_valid_led_default(hw, &data); in igb_id_led_init()
1412 if (ret_val) in igb_id_led_init()
1458 return ret_val; in igb_id_led_init()
1553 s32 ret_val = 0; in igb_disable_pcie_master() local
1572 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; in igb_disable_pcie_master()
1577 return ret_val; in igb_disable_pcie_master()
1589 s32 ret_val = 0; in igb_validate_mdi_setting() local
1598 ret_val = -E1000_ERR_CONFIG; in igb_validate_mdi_setting()
1603 return ret_val; in igb_validate_mdi_setting()
1621 s32 ret_val = 0; in igb_write_8bit_ctrl_reg() local
1636 ret_val = -E1000_ERR_PHY; in igb_write_8bit_ctrl_reg()
1641 return ret_val; in igb_write_8bit_ctrl_reg()
1655 bool ret_val = false; in igb_enable_mng_pass_thru() local
1672 ret_val = true; in igb_enable_mng_pass_thru()
1678 ret_val = true; in igb_enable_mng_pass_thru()
1684 return ret_val; in igb_enable_mng_pass_thru()