Lines Matching defs:channel
89 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
90 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
91 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
94 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
95 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
96 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
218 #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) argument
220 #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) argument
241 #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ argument
245 #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ argument
274 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ argument
283 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ argument
285 #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) argument
303 #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) argument
304 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) argument
305 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) argument
306 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) argument
367 #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) argument
368 #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) argument
369 #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) argument
370 #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) argument
371 #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) argument
372 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) argument
377 #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) argument
378 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) argument
380 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) argument
393 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) argument
401 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) argument
403 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) argument
405 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) argument
407 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) argument
409 #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) argument
411 #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) argument
415 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) argument
421 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) argument
435 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) argument
439 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) argument
441 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) argument
443 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) argument
445 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) argument
447 #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) argument
449 #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) argument
454 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) argument
731 #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) argument