Lines Matching refs:idx
218 int idx, jdx; in sparx5_create_targets() local
220 for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { in sparx5_create_targets()
223 if (idx == iomap->range) { in sparx5_create_targets()
224 range_id[idx] = jdx; in sparx5_create_targets()
225 idx++; in sparx5_create_targets()
228 for (idx = 0; idx < IO_RANGES; idx++) { in sparx5_create_targets()
229 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, in sparx5_create_targets()
230 idx); in sparx5_create_targets()
231 if (!iores[idx]) { in sparx5_create_targets()
235 iomem[idx] = devm_ioremap(sparx5->dev, in sparx5_create_targets()
236 iores[idx]->start, in sparx5_create_targets()
237 resource_size(iores[idx])); in sparx5_create_targets()
238 if (!iomem[idx]) { in sparx5_create_targets()
240 iores[idx]->name); in sparx5_create_targets()
243 begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset; in sparx5_create_targets()
324 u32 value, pending, jdx, idx; in sparx5_init_ram() local
328 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) { in sparx5_init_ram()
329 cfg = &spx5_ram_cfg[idx]; in sparx5_init_ram()
389 u32 clk_div, clk_period, pol_upd_int, idx; in sparx5_init_coreclock() local
495 for (idx = 0; idx < 3; idx++) in sparx5_init_coreclock()
499 GCB_SIO_CLOCK(idx)); in sparx5_init_coreclock()
543 int idx; in sparx5_board_init() local
555 for (idx = 0; idx < SPX5_PORTS; idx++) in sparx5_board_init()
556 if (sparx5->ports[idx]) in sparx5_board_init()
557 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) in sparx5_board_init()
558 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, in sparx5_board_init()
560 GCB_HW_SGPIO_TO_SD_MAP_CFG(idx)); in sparx5_board_init()
567 u32 idx; in sparx5_start() local
571 for (idx = 0; idx < 3; idx++) { in sparx5_start()
572 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); in sparx5_start()
573 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); in sparx5_start()
574 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); in sparx5_start()
575 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx)); in sparx5_start()
579 for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++) in sparx5_start()
583 QFWD_SWITCH_PORT_MODE(idx)); in sparx5_start()
595 for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++) in sparx5_start()
598 sparx5, ANA_CL_FILTER_CTRL(idx)); in sparx5_start()
686 int idx = 0, err = 0; in mchp_sparx5_probe() local
733 config = &configs[idx]; in mchp_sparx5_probe()
771 idx++; in mchp_sparx5_probe()
807 for (idx = 0; idx < sparx5->port_count; ++idx) { in mchp_sparx5_probe()
808 config = &configs[idx]; in mchp_sparx5_probe()