Lines Matching refs:plat
64 int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
65 int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
81 static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat) in mt2712_set_interface() argument
83 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
84 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
94 plat->num_clks_to_config = plat->variant->num_clks - 1; in mt2712_set_interface()
97 switch (plat->phy_mode) { in mt2712_set_interface()
102 if (plat->rmii_clk_from_mac) in mt2712_set_interface()
103 plat->num_clks_to_config++; in mt2712_set_interface()
113 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
117 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
122 static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) in mt2712_delay_ps2stage() argument
124 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
126 switch (plat->phy_mode) { in mt2712_delay_ps2stage()
142 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_delay_ps2stage()
147 static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) in mt2712_delay_stage2ps() argument
149 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_stage2ps()
151 switch (plat->phy_mode) { in mt2712_delay_stage2ps()
167 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_delay_stage2ps()
172 static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat) in mt2712_set_delay() argument
174 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_set_delay()
177 mt2712_delay_ps2stage(plat); in mt2712_set_delay()
179 switch (plat->phy_mode) { in mt2712_set_delay()
190 if (plat->rmii_clk_from_mac) { in mt2712_set_delay()
210 if (plat->rmii_rxc) { in mt2712_set_delay()
250 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_delay()
253 regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val); in mt2712_set_delay()
254 regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val); in mt2712_set_delay()
256 mt2712_delay_stage2ps(plat); in mt2712_set_delay()
271 static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat) in mediatek_dwmac_config_dt() argument
273 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mediatek_dwmac_config_dt()
277 plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg"); in mediatek_dwmac_config_dt()
278 if (IS_ERR(plat->peri_regmap)) { in mediatek_dwmac_config_dt()
279 dev_err(plat->dev, "Failed to get pericfg syscon\n"); in mediatek_dwmac_config_dt()
280 return PTR_ERR(plat->peri_regmap); in mediatek_dwmac_config_dt()
283 err = of_get_phy_mode(plat->np, &plat->phy_mode); in mediatek_dwmac_config_dt()
285 dev_err(plat->dev, "not find phy-mode\n"); in mediatek_dwmac_config_dt()
289 if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) { in mediatek_dwmac_config_dt()
290 if (tx_delay_ps < plat->variant->tx_delay_max) { in mediatek_dwmac_config_dt()
293 dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps); in mediatek_dwmac_config_dt()
298 if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) { in mediatek_dwmac_config_dt()
299 if (rx_delay_ps < plat->variant->rx_delay_max) { in mediatek_dwmac_config_dt()
302 dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps); in mediatek_dwmac_config_dt()
307 mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse"); in mediatek_dwmac_config_dt()
308 mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse"); in mediatek_dwmac_config_dt()
309 plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc"); in mediatek_dwmac_config_dt()
310 plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac"); in mediatek_dwmac_config_dt()
315 static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat) in mediatek_dwmac_clk_init() argument
317 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_clk_init()
320 plat->clks = devm_kcalloc(plat->dev, num, sizeof(*plat->clks), GFP_KERNEL); in mediatek_dwmac_clk_init()
321 if (!plat->clks) in mediatek_dwmac_clk_init()
325 plat->clks[i].id = variant->clk_list[i]; in mediatek_dwmac_clk_init()
327 plat->num_clks_to_config = variant->num_clks; in mediatek_dwmac_clk_init()
329 return devm_clk_bulk_get(plat->dev, num, plat->clks); in mediatek_dwmac_clk_init()
334 struct mediatek_dwmac_plat_data *plat = priv; in mediatek_dwmac_init() local
335 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_init()
338 ret = dma_set_mask_and_coherent(plat->dev, DMA_BIT_MASK(variant->dma_bit_mask)); in mediatek_dwmac_init()
340 dev_err(plat->dev, "No suitable DMA available, err = %d\n", ret); in mediatek_dwmac_init()
344 ret = variant->dwmac_set_phy_interface(plat); in mediatek_dwmac_init()
346 dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret); in mediatek_dwmac_init()
350 ret = variant->dwmac_set_delay(plat); in mediatek_dwmac_init()
352 dev_err(plat->dev, "failed to set delay value, err = %d\n", ret); in mediatek_dwmac_init()
356 ret = clk_bulk_prepare_enable(plat->num_clks_to_config, plat->clks); in mediatek_dwmac_init()
358 dev_err(plat->dev, "failed to enable clks, err = %d\n", ret); in mediatek_dwmac_init()
370 struct mediatek_dwmac_plat_data *plat = priv; in mediatek_dwmac_exit() local
372 clk_bulk_disable_unprepare(plat->num_clks_to_config, plat->clks); in mediatek_dwmac_exit()