Lines Matching refs:lp
24 static int axienet_mdio_wait_until_ready(struct axienet_local *lp) in axienet_mdio_wait_until_ready() argument
28 return readx_poll_timeout(axinet_ior_read_mcr, lp, in axienet_mdio_wait_until_ready()
34 static void axienet_mdio_mdc_enable(struct axienet_local *lp) in axienet_mdio_mdc_enable() argument
36 axienet_iow(lp, XAE_MDIO_MC_OFFSET, in axienet_mdio_mdc_enable()
37 ((u32)lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK)); in axienet_mdio_mdc_enable()
41 static void axienet_mdio_mdc_disable(struct axienet_local *lp) in axienet_mdio_mdc_disable() argument
45 mc_reg = axienet_ior(lp, XAE_MDIO_MC_OFFSET); in axienet_mdio_mdc_disable()
46 axienet_iow(lp, XAE_MDIO_MC_OFFSET, in axienet_mdio_mdc_disable()
66 struct axienet_local *lp = bus->priv; in axienet_mdio_read() local
68 axienet_mdio_mdc_enable(lp); in axienet_mdio_read()
70 ret = axienet_mdio_wait_until_ready(lp); in axienet_mdio_read()
72 axienet_mdio_mdc_disable(lp); in axienet_mdio_read()
76 axienet_iow(lp, XAE_MDIO_MCR_OFFSET, in axienet_mdio_read()
84 ret = axienet_mdio_wait_until_ready(lp); in axienet_mdio_read()
86 axienet_mdio_mdc_disable(lp); in axienet_mdio_read()
90 rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF; in axienet_mdio_read()
92 dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n", in axienet_mdio_read()
95 axienet_mdio_mdc_disable(lp); in axienet_mdio_read()
116 struct axienet_local *lp = bus->priv; in axienet_mdio_write() local
118 dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n", in axienet_mdio_write()
121 axienet_mdio_mdc_enable(lp); in axienet_mdio_write()
123 ret = axienet_mdio_wait_until_ready(lp); in axienet_mdio_write()
125 axienet_mdio_mdc_disable(lp); in axienet_mdio_write()
129 axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val); in axienet_mdio_write()
130 axienet_iow(lp, XAE_MDIO_MCR_OFFSET, in axienet_mdio_write()
138 ret = axienet_mdio_wait_until_ready(lp); in axienet_mdio_write()
140 axienet_mdio_mdc_disable(lp); in axienet_mdio_write()
143 axienet_mdio_mdc_disable(lp); in axienet_mdio_write()
156 int axienet_mdio_enable(struct axienet_local *lp) in axienet_mdio_enable() argument
160 lp->mii_clk_div = 0; in axienet_mdio_enable()
162 if (lp->axi_clk) { in axienet_mdio_enable()
163 host_clock = clk_get_rate(lp->axi_clk); in axienet_mdio_enable()
172 netdev_warn(lp->ndev, "Could not find CPU device node.\n"); in axienet_mdio_enable()
178 netdev_warn(lp->ndev, "CPU clock-frequency property not found.\n"); in axienet_mdio_enable()
183 netdev_info(lp->ndev, "Setting assumed host clock to %u\n", in axienet_mdio_enable()
212 lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1; in axienet_mdio_enable()
218 lp->mii_clk_div++; in axienet_mdio_enable()
220 netdev_dbg(lp->ndev, in axienet_mdio_enable()
222 lp->mii_clk_div, host_clock); in axienet_mdio_enable()
224 axienet_iow(lp, XAE_MDIO_MC_OFFSET, lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK); in axienet_mdio_enable()
226 return axienet_mdio_wait_until_ready(lp); in axienet_mdio_enable()
235 void axienet_mdio_disable(struct axienet_local *lp) in axienet_mdio_disable() argument
237 axienet_iow(lp, XAE_MDIO_MC_OFFSET, 0); in axienet_mdio_disable()
250 int axienet_mdio_setup(struct axienet_local *lp) in axienet_mdio_setup() argument
256 ret = axienet_mdio_enable(lp); in axienet_mdio_setup()
265 (unsigned long long)lp->regs_start); in axienet_mdio_setup()
267 bus->priv = lp; in axienet_mdio_setup()
271 bus->parent = lp->dev; in axienet_mdio_setup()
272 lp->mii_bus = bus; in axienet_mdio_setup()
274 mdio_node = of_get_child_by_name(lp->dev->of_node, "mdio"); in axienet_mdio_setup()
279 lp->mii_bus = NULL; in axienet_mdio_setup()
282 axienet_mdio_mdc_disable(lp); in axienet_mdio_setup()
292 void axienet_mdio_teardown(struct axienet_local *lp) in axienet_mdio_teardown() argument
294 mdiobus_unregister(lp->mii_bus); in axienet_mdio_teardown()
295 mdiobus_free(lp->mii_bus); in axienet_mdio_teardown()
296 lp->mii_bus = NULL; in axienet_mdio_teardown()