Lines Matching refs:phydev
15 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) in genphy_c45_pma_can_sleep() argument
19 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); in genphy_c45_pma_can_sleep()
30 int genphy_c45_pma_resume(struct phy_device *phydev) in genphy_c45_pma_resume() argument
32 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_resume()
35 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume()
44 int genphy_c45_pma_suspend(struct phy_device *phydev) in genphy_c45_pma_suspend() argument
46 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_suspend()
49 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_suspend()
58 int genphy_c45_pma_setup_forced(struct phy_device *phydev) in genphy_c45_pma_setup_forced() argument
63 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
66 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_pma_setup_forced()
70 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); in genphy_c45_pma_setup_forced()
81 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
113 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
117 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
121 return genphy_c45_an_disable_aneg(phydev); in genphy_c45_pma_setup_forced()
134 int genphy_c45_an_config_aneg(struct phy_device *phydev) in genphy_c45_an_config_aneg() argument
139 linkmode_and(phydev->advertising, phydev->advertising, in genphy_c45_an_config_aneg()
140 phydev->supported); in genphy_c45_an_config_aneg()
142 changed = genphy_config_eee_advert(phydev); in genphy_c45_an_config_aneg()
144 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
146 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in genphy_c45_an_config_aneg()
155 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
157 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_an_config_aneg()
179 int genphy_c45_an_disable_aneg(struct phy_device *phydev) in genphy_c45_an_disable_aneg() argument
182 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, in genphy_c45_an_disable_aneg()
195 int genphy_c45_restart_aneg(struct phy_device *phydev) in genphy_c45_restart_aneg() argument
197 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, in genphy_c45_restart_aneg()
211 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) in genphy_c45_check_and_restart_aneg() argument
217 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_check_and_restart_aneg()
226 return genphy_c45_restart_aneg(phydev); in genphy_c45_check_and_restart_aneg()
243 int genphy_c45_aneg_done(struct phy_device *phydev) in genphy_c45_aneg_done() argument
245 int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_aneg_done()
259 int genphy_c45_read_link(struct phy_device *phydev) in genphy_c45_read_link() argument
265 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_read_link()
266 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
274 phydev->link = 0; in genphy_c45_read_link()
288 if (!phy_polling_mode(phydev) || !phydev->link) { in genphy_c45_read_link()
289 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
296 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
304 phydev->link = link; in genphy_c45_read_link()
320 int genphy_c45_read_lpa(struct phy_device *phydev) in genphy_c45_read_lpa() argument
324 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_read_lpa()
330 phydev->lp_advertising); in genphy_c45_read_lpa()
331 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
332 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
333 phydev->pause = 0; in genphy_c45_read_lpa()
334 phydev->asym_pause = 0; in genphy_c45_read_lpa()
339 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, in genphy_c45_read_lpa()
343 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in genphy_c45_read_lpa()
347 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
348 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; in genphy_c45_read_lpa()
349 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; in genphy_c45_read_lpa()
352 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in genphy_c45_read_lpa()
356 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
366 int genphy_c45_read_pma(struct phy_device *phydev) in genphy_c45_read_pma() argument
370 linkmode_zero(phydev->lp_advertising); in genphy_c45_read_pma()
372 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_read_pma()
378 phydev->speed = SPEED_10; in genphy_c45_read_pma()
381 phydev->speed = SPEED_100; in genphy_c45_read_pma()
384 phydev->speed = SPEED_1000; in genphy_c45_read_pma()
387 phydev->speed = SPEED_2500; in genphy_c45_read_pma()
390 phydev->speed = SPEED_5000; in genphy_c45_read_pma()
393 phydev->speed = SPEED_10000; in genphy_c45_read_pma()
396 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_pma()
400 phydev->duplex = DUPLEX_FULL; in genphy_c45_read_pma()
410 int genphy_c45_read_mdix(struct phy_device *phydev) in genphy_c45_read_mdix() argument
414 if (phydev->speed == SPEED_10000) { in genphy_c45_read_mdix()
415 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_read_mdix()
422 phydev->mdix = ETH_TP_MDI; in genphy_c45_read_mdix()
426 phydev->mdix = ETH_TP_MDI_X; in genphy_c45_read_mdix()
430 phydev->mdix = ETH_TP_MDI_INVALID; in genphy_c45_read_mdix()
450 int genphy_c45_pma_read_abilities(struct phy_device *phydev) in genphy_c45_pma_read_abilities() argument
454 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); in genphy_c45_pma_read_abilities()
455 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_pma_read_abilities()
456 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_pma_read_abilities()
462 phydev->supported); in genphy_c45_pma_read_abilities()
465 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); in genphy_c45_pma_read_abilities()
470 phydev->supported, in genphy_c45_pma_read_abilities()
474 phydev->supported, in genphy_c45_pma_read_abilities()
478 phydev->supported, in genphy_c45_pma_read_abilities()
482 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_pma_read_abilities()
487 phydev->supported, in genphy_c45_pma_read_abilities()
490 phydev->supported, in genphy_c45_pma_read_abilities()
493 phydev->supported, in genphy_c45_pma_read_abilities()
496 phydev->supported, in genphy_c45_pma_read_abilities()
499 phydev->supported, in genphy_c45_pma_read_abilities()
502 phydev->supported, in genphy_c45_pma_read_abilities()
506 phydev->supported, in genphy_c45_pma_read_abilities()
509 phydev->supported, in genphy_c45_pma_read_abilities()
513 phydev->supported, in genphy_c45_pma_read_abilities()
516 phydev->supported, in genphy_c45_pma_read_abilities()
520 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_pma_read_abilities()
526 phydev->supported, in genphy_c45_pma_read_abilities()
530 phydev->supported, in genphy_c45_pma_read_abilities()
545 int genphy_c45_read_status(struct phy_device *phydev) in genphy_c45_read_status() argument
549 ret = genphy_c45_read_link(phydev); in genphy_c45_read_status()
553 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_status()
554 phydev->duplex = DUPLEX_UNKNOWN; in genphy_c45_read_status()
555 phydev->pause = 0; in genphy_c45_read_status()
556 phydev->asym_pause = 0; in genphy_c45_read_status()
558 if (phydev->autoneg == AUTONEG_ENABLE) { in genphy_c45_read_status()
559 ret = genphy_c45_read_lpa(phydev); in genphy_c45_read_status()
563 phy_resolve_aneg_linkmode(phydev); in genphy_c45_read_status()
565 ret = genphy_c45_read_pma(phydev); in genphy_c45_read_status()
580 int genphy_c45_config_aneg(struct phy_device *phydev) in genphy_c45_config_aneg() argument
585 if (phydev->autoneg == AUTONEG_DISABLE) in genphy_c45_config_aneg()
586 return genphy_c45_pma_setup_forced(phydev); in genphy_c45_config_aneg()
588 ret = genphy_c45_an_config_aneg(phydev); in genphy_c45_config_aneg()
594 return genphy_c45_check_and_restart_aneg(phydev, changed); in genphy_c45_config_aneg()
600 int gen10g_config_aneg(struct phy_device *phydev) in gen10g_config_aneg() argument
606 int genphy_c45_loopback(struct phy_device *phydev, bool enable) in genphy_c45_loopback() argument
608 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, in genphy_c45_loopback()
624 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) in genphy_c45_fast_retrain() argument
629 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
632 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { in genphy_c45_fast_retrain()
633 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_fast_retrain()
638 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, in genphy_c45_fast_retrain()
644 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()