Lines Matching refs:child

144 	struct pci_dev *child;  in pcie_set_clkpm_nocheck()  local
148 	list_for_each_entry(child, &linkbus->devices, bus_list)  in pcie_set_clkpm_nocheck()
149 		pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,  in pcie_set_clkpm_nocheck()
174 	struct pci_dev *child;  in pcie_clkpm_cap_init()  local
178 	list_for_each_entry(child, &linkbus->devices, bus_list) {  in pcie_clkpm_cap_init()
179 		pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);  in pcie_clkpm_cap_init()
185 		pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);  in pcie_clkpm_cap_init()
234 	struct pci_dev *child, *parent = link->pdev;  in pcie_aspm_configure_common_clock()  local
240 	child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);  in pcie_aspm_configure_common_clock()
241 	BUG_ON(!pci_is_pcie(child));  in pcie_aspm_configure_common_clock()
244 	pcie_capability_read_word(child, PCI_EXP_LNKSTA, &reg16);  in pcie_aspm_configure_common_clock()
258 		list_for_each_entry(child, &linkbus->devices, bus_list) {  in pcie_aspm_configure_common_clock()
259 			pcie_capability_read_word(child, PCI_EXP_LNKCTL,  in pcie_aspm_configure_common_clock()
272 	list_for_each_entry(child, &linkbus->devices, bus_list) {  in pcie_aspm_configure_common_clock()
273 		pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);  in pcie_aspm_configure_common_clock()
274 		child_reg[PCI_FUNC(child->devfn)] = reg16;  in pcie_aspm_configure_common_clock()
279 		pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);  in pcie_aspm_configure_common_clock()
296 	list_for_each_entry(child, &linkbus->devices, bus_list)  in pcie_aspm_configure_common_clock()
297 		pcie_capability_write_word(child, PCI_EXP_LNKCTL,  in pcie_aspm_configure_common_clock()
298 					   child_reg[PCI_FUNC(child->devfn)]);  in pcie_aspm_configure_common_clock()
432 	struct pci_dev *child;  in pci_function_0()  local
434 	list_for_each_entry(child, &linkbus->devices, bus_list)  in pci_function_0()
435 		if (PCI_FUNC(child->devfn) == 0)  in pci_function_0()
436 			return child;  in pci_function_0()
455 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in aspm_calc_l1ss_info()  local
477 	    calc_l1ss_pwron(child, scale2, val2)) {  in aspm_calc_l1ss_info()
482 		t_power_on = calc_l1ss_pwron(child, scale2, val2);  in aspm_calc_l1ss_info()
501 	pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);  in aspm_calc_l1ss_info()
502 	pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);  in aspm_calc_l1ss_info()
513 		pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,  in aspm_calc_l1ss_info()
521 	pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);  in aspm_calc_l1ss_info()
531 	pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,  in aspm_calc_l1ss_info()
538 		pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,  in aspm_calc_l1ss_info()
545 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_aspm_cap_init()  local
564 	pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);  in pcie_aspm_cap_init()
578 	pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);  in pcie_aspm_cap_init()
580 	pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);  in pcie_aspm_cap_init()
611 	pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,  in pcie_aspm_cap_init()
624 	if (!child->ltr_path)  in pcie_aspm_cap_init()
640 		pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,  in pcie_aspm_cap_init()
662 	list_for_each_entry(child, &linkbus->devices, bus_list) {  in pcie_aspm_cap_init()
665 			&link->acceptable[PCI_FUNC(child->devfn)];  in pcie_aspm_cap_init()
667 		if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&  in pcie_aspm_cap_init()
668 		    pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)  in pcie_aspm_cap_init()
671 		pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);  in pcie_aspm_cap_init()
679 		pcie_aspm_check_latency(child);  in pcie_aspm_cap_init()
687 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_config_aspm_l1ss()  local
705 	pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,  in pcie_config_aspm_l1ss()
714 		pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,  in pcie_config_aspm_l1ss()
733 	pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,  in pcie_config_aspm_l1ss()
746 	struct pci_dev *child = link->downstream, *parent = link->pdev;  in pcie_config_aspm_link()  local
757 	if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {  in pcie_config_aspm_link()
786 	list_for_each_entry(child, &linkbus->devices, bus_list)  in pcie_config_aspm_link()
787 		pcie_config_aspm_dev(child, dwstream);  in pcie_config_aspm_link()
810 	struct pci_dev *child;  in pcie_aspm_sanity_check()  local
817 	list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {  in pcie_aspm_sanity_check()
818 		if (!pci_is_pcie(child))  in pcie_aspm_sanity_check()
834 		pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);  in pcie_aspm_sanity_check()
836 …pci_info(child, "disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\…  in pcie_aspm_sanity_check()
886 	struct pci_dev *child;  in pcie_aspm_update_sysfs_visibility()  local
888 	list_for_each_entry(child, &pdev->subordinate->devices, bus_list)  in pcie_aspm_update_sysfs_visibility()
889 		sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group);  in pcie_aspm_update_sysfs_visibility()
972 		struct pci_dev *child;  in pcie_update_aspm_capable()  local
976 		list_for_each_entry(child, &linkbus->devices, bus_list) {  in pcie_update_aspm_capable()
977 			if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&  in pcie_update_aspm_capable()
978 			    (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))  in pcie_update_aspm_capable()
980 			pcie_aspm_check_latency(child);  in pcie_update_aspm_capable()