Lines Matching refs:tmp
365 u32 tmp; in hs_slew_rate_calibrate() local
376 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
377 tmp |= PA5_RG_U2_HSTX_SRCAL_EN; in hs_slew_rate_calibrate()
378 writel(tmp, com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
382 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
383 tmp |= P2F_RG_FRCK_EN; in hs_slew_rate_calibrate()
384 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
387 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
388 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); in hs_slew_rate_calibrate()
389 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); in hs_slew_rate_calibrate()
391 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); in hs_slew_rate_calibrate()
393 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
396 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
397 tmp |= P2F_RG_FREQDET_EN; in hs_slew_rate_calibrate()
398 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
401 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, in hs_slew_rate_calibrate()
402 (tmp & P2F_USB_FM_VALID), 10, 200); in hs_slew_rate_calibrate()
407 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
408 tmp &= ~P2F_RG_FREQDET_EN; in hs_slew_rate_calibrate()
409 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
412 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
413 tmp &= ~P2F_RG_FRCK_EN; in hs_slew_rate_calibrate()
414 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
418 tmp = tphy->src_ref_clk * tphy->src_coef; in hs_slew_rate_calibrate()
419 tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out; in hs_slew_rate_calibrate()
420 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); in hs_slew_rate_calibrate()
430 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
431 tmp &= ~PA5_RG_U2_HSTX_SRCTRL; in hs_slew_rate_calibrate()
432 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val); in hs_slew_rate_calibrate()
433 writel(tmp, com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
436 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
437 tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN; in hs_slew_rate_calibrate()
438 writel(tmp, com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
445 u32 tmp; in u3_phy_instance_init() local
448 tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3); in u3_phy_instance_init()
449 tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD; in u3_phy_instance_init()
450 writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3); in u3_phy_instance_init()
453 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); in u3_phy_instance_init()
454 tmp &= ~P3A_RG_XTAL_EXT_EN_U3; in u3_phy_instance_init()
455 tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2); in u3_phy_instance_init()
456 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); in u3_phy_instance_init()
458 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9); in u3_phy_instance_init()
459 tmp &= ~P3A_RG_RX_DAC_MUX; in u3_phy_instance_init()
460 tmp |= P3A_RG_RX_DAC_MUX_VAL(4); in u3_phy_instance_init()
461 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9); in u3_phy_instance_init()
463 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6); in u3_phy_instance_init()
464 tmp &= ~P3A_RG_TX_EIDLE_CM; in u3_phy_instance_init()
465 tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe); in u3_phy_instance_init()
466 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6); in u3_phy_instance_init()
468 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1); in u3_phy_instance_init()
469 tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1); in u3_phy_instance_init()
470 tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3); in u3_phy_instance_init()
471 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1); in u3_phy_instance_init()
473 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1); in u3_phy_instance_init()
474 tmp &= ~P3D_RG_FWAKE_TH; in u3_phy_instance_init()
475 tmp |= P3D_RG_FWAKE_TH_VAL(0x34); in u3_phy_instance_init()
476 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1); in u3_phy_instance_init()
478 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); in u3_phy_instance_init()
479 tmp &= ~P3D_RG_RXDET_STB2_SET; in u3_phy_instance_init()
480 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); in u3_phy_instance_init()
481 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); in u3_phy_instance_init()
483 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); in u3_phy_instance_init()
484 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; in u3_phy_instance_init()
485 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); in u3_phy_instance_init()
486 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); in u3_phy_instance_init()
496 u32 tmp; in u2_phy_pll_26m_set() local
501 tmp = readl(com + U3P_USBPHYACR0); in u2_phy_pll_26m_set()
502 tmp &= ~PA0_USB20_PLL_PREDIV; in u2_phy_pll_26m_set()
503 tmp |= PA0_USB20_PLL_PREDIV_VAL(0); in u2_phy_pll_26m_set()
504 writel(tmp, com + U3P_USBPHYACR0); in u2_phy_pll_26m_set()
506 tmp = readl(com + U3P_USBPHYACR2); in u2_phy_pll_26m_set()
507 tmp &= ~PA2_RG_U2PLL_BW; in u2_phy_pll_26m_set()
508 tmp |= PA2_RG_U2PLL_BW_VAL(3); in u2_phy_pll_26m_set()
509 writel(tmp, com + U3P_USBPHYACR2); in u2_phy_pll_26m_set()
513 tmp = readl(com + U3P_U2PHYA_RESV1); in u2_phy_pll_26m_set()
514 tmp |= P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL; in u2_phy_pll_26m_set()
515 writel(tmp, com + U3P_U2PHYA_RESV1); in u2_phy_pll_26m_set()
524 u32 tmp; in u2_phy_instance_init() local
527 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_init()
528 tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM); in u2_phy_instance_init()
529 tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0); in u2_phy_instance_init()
530 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_init()
532 tmp = readl(com + U3P_U2PHYDTM1); in u2_phy_instance_init()
533 tmp &= ~P2C_RG_UART_EN; in u2_phy_instance_init()
534 writel(tmp, com + U3P_U2PHYDTM1); in u2_phy_instance_init()
536 tmp = readl(com + U3P_USBPHYACR0); in u2_phy_instance_init()
537 tmp |= PA0_RG_USB20_INTR_EN; in u2_phy_instance_init()
538 writel(tmp, com + U3P_USBPHYACR0); in u2_phy_instance_init()
541 tmp = readl(com + U3P_USBPHYACR5); in u2_phy_instance_init()
542 tmp &= ~PA5_RG_U2_HS_100U_U3_EN; in u2_phy_instance_init()
543 writel(tmp, com + U3P_USBPHYACR5); in u2_phy_instance_init()
546 tmp = readl(com + U3P_U2PHYACR4); in u2_phy_instance_init()
547 tmp &= ~P2C_U2_GPIO_CTR_MSK; in u2_phy_instance_init()
548 writel(tmp, com + U3P_U2PHYACR4); in u2_phy_instance_init()
553 tmp = readl(com + U3P_USBPHYACR2); in u2_phy_instance_init()
554 tmp |= PA2_RG_SIF_U2PLL_FORCE_EN; in u2_phy_instance_init()
555 writel(tmp, com + U3P_USBPHYACR2); in u2_phy_instance_init()
557 tmp = readl(com + U3D_U2PHYDCR0); in u2_phy_instance_init()
558 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; in u2_phy_instance_init()
559 writel(tmp, com + U3D_U2PHYDCR0); in u2_phy_instance_init()
561 tmp = readl(com + U3D_U2PHYDCR0); in u2_phy_instance_init()
562 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; in u2_phy_instance_init()
563 writel(tmp, com + U3D_U2PHYDCR0); in u2_phy_instance_init()
565 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_init()
566 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; in u2_phy_instance_init()
567 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_init()
571 tmp = readl(com + U3P_USBPHYACR6); in u2_phy_instance_init()
572 tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */ in u2_phy_instance_init()
573 tmp &= ~PA6_RG_U2_SQTH; in u2_phy_instance_init()
574 tmp |= PA6_RG_U2_SQTH_VAL(2); in u2_phy_instance_init()
575 writel(tmp, com + U3P_USBPHYACR6); in u2_phy_instance_init()
589 u32 tmp; in u2_phy_instance_power_on() local
591 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_power_on()
592 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); in u2_phy_instance_power_on()
593 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_power_on()
596 tmp = readl(com + U3P_USBPHYACR6); in u2_phy_instance_power_on()
597 tmp |= PA6_RG_U2_OTG_VBUSCMP_EN; in u2_phy_instance_power_on()
598 writel(tmp, com + U3P_USBPHYACR6); in u2_phy_instance_power_on()
600 tmp = readl(com + U3P_U2PHYDTM1); in u2_phy_instance_power_on()
601 tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID; in u2_phy_instance_power_on()
602 tmp &= ~P2C_RG_SESSEND; in u2_phy_instance_power_on()
603 writel(tmp, com + U3P_U2PHYDTM1); in u2_phy_instance_power_on()
606 tmp = readl(com + U3D_U2PHYDCR0); in u2_phy_instance_power_on()
607 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; in u2_phy_instance_power_on()
608 writel(tmp, com + U3D_U2PHYDCR0); in u2_phy_instance_power_on()
610 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_power_on()
611 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; in u2_phy_instance_power_on()
612 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_power_on()
623 u32 tmp; in u2_phy_instance_power_off() local
625 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_power_off()
626 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN); in u2_phy_instance_power_off()
627 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_power_off()
630 tmp = readl(com + U3P_USBPHYACR6); in u2_phy_instance_power_off()
631 tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; in u2_phy_instance_power_off()
632 writel(tmp, com + U3P_USBPHYACR6); in u2_phy_instance_power_off()
634 tmp = readl(com + U3P_U2PHYDTM1); in u2_phy_instance_power_off()
635 tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID); in u2_phy_instance_power_off()
636 tmp |= P2C_RG_SESSEND; in u2_phy_instance_power_off()
637 writel(tmp, com + U3P_U2PHYDTM1); in u2_phy_instance_power_off()
640 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_power_off()
641 tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); in u2_phy_instance_power_off()
642 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_power_off()
644 tmp = readl(com + U3D_U2PHYDCR0); in u2_phy_instance_power_off()
645 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; in u2_phy_instance_power_off()
646 writel(tmp, com + U3D_U2PHYDCR0); in u2_phy_instance_power_off()
658 u32 tmp; in u2_phy_instance_exit() local
661 tmp = readl(com + U3D_U2PHYDCR0); in u2_phy_instance_exit()
662 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; in u2_phy_instance_exit()
663 writel(tmp, com + U3D_U2PHYDCR0); in u2_phy_instance_exit()
665 tmp = readl(com + U3P_U2PHYDTM0); in u2_phy_instance_exit()
666 tmp &= ~P2C_FORCE_SUSPENDM; in u2_phy_instance_exit()
667 writel(tmp, com + U3P_U2PHYDTM0); in u2_phy_instance_exit()
676 u32 tmp; in u2_phy_instance_set_mode() local
678 tmp = readl(u2_banks->com + U3P_U2PHYDTM1); in u2_phy_instance_set_mode()
681 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG; in u2_phy_instance_set_mode()
684 tmp |= P2C_FORCE_IDDIG; in u2_phy_instance_set_mode()
685 tmp &= ~P2C_RG_IDDIG; in u2_phy_instance_set_mode()
688 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG); in u2_phy_instance_set_mode()
693 writel(tmp, u2_banks->com + U3P_U2PHYDTM1); in u2_phy_instance_set_mode()
700 u32 tmp; in pcie_phy_instance_init() local
705 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); in pcie_phy_instance_init()
706 tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); in pcie_phy_instance_init()
707 tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); in pcie_phy_instance_init()
708 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); in pcie_phy_instance_init()
711 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); in pcie_phy_instance_init()
712 tmp &= ~P3A_RG_CLKDRV_AMP; in pcie_phy_instance_init()
713 tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4); in pcie_phy_instance_init()
714 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); in pcie_phy_instance_init()
716 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); in pcie_phy_instance_init()
717 tmp &= ~P3A_RG_CLKDRV_OFF; in pcie_phy_instance_init()
718 tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1); in pcie_phy_instance_init()
719 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); in pcie_phy_instance_init()
722 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); in pcie_phy_instance_init()
723 tmp &= ~P3A_RG_PLL_DELTA1_PE2H; in pcie_phy_instance_init()
724 tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c); in pcie_phy_instance_init()
725 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); in pcie_phy_instance_init()
727 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); in pcie_phy_instance_init()
728 tmp &= ~P3A_RG_PLL_DELTA_PE2H; in pcie_phy_instance_init()
729 tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36); in pcie_phy_instance_init()
730 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); in pcie_phy_instance_init()
733 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); in pcie_phy_instance_init()
734 tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H); in pcie_phy_instance_init()
735 tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1); in pcie_phy_instance_init()
736 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); in pcie_phy_instance_init()
738 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); in pcie_phy_instance_init()
739 tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H); in pcie_phy_instance_init()
740 tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3); in pcie_phy_instance_init()
741 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); in pcie_phy_instance_init()
743 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); in pcie_phy_instance_init()
744 tmp &= ~P3A_RG_PLL_IR_PE2H; in pcie_phy_instance_init()
745 tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2); in pcie_phy_instance_init()
746 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); in pcie_phy_instance_init()
748 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); in pcie_phy_instance_init()
749 tmp &= ~P3A_RG_PLL_BP_PE2H; in pcie_phy_instance_init()
750 tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa); in pcie_phy_instance_init()
751 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); in pcie_phy_instance_init()
754 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); in pcie_phy_instance_init()
755 tmp &= ~P3D_RG_RXDET_STB2_SET; in pcie_phy_instance_init()
756 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); in pcie_phy_instance_init()
757 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); in pcie_phy_instance_init()
759 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); in pcie_phy_instance_init()
760 tmp &= ~P3D_RG_RXDET_STB2_SET_P3; in pcie_phy_instance_init()
761 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); in pcie_phy_instance_init()
762 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); in pcie_phy_instance_init()
773 u32 tmp; in pcie_phy_instance_power_on() local
775 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_on()
776 tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); in pcie_phy_instance_power_on()
777 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_on()
779 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_on()
780 tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); in pcie_phy_instance_power_on()
781 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_on()
789 u32 tmp; in pcie_phy_instance_power_off() local
791 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_off()
792 tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST; in pcie_phy_instance_power_off()
793 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_off()
795 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_off()
796 tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD; in pcie_phy_instance_power_off()
797 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_off()
805 u32 tmp; in sata_phy_instance_init() local
808 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6); in sata_phy_instance_init()
809 tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK); in sata_phy_instance_init()
810 tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a); in sata_phy_instance_init()
811 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6); in sata_phy_instance_init()
813 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4); in sata_phy_instance_init()
814 tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK; in sata_phy_instance_init()
815 tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18); in sata_phy_instance_init()
816 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4); in sata_phy_instance_init()
818 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5); in sata_phy_instance_init()
819 tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK; in sata_phy_instance_init()
820 tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06); in sata_phy_instance_init()
821 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5); in sata_phy_instance_init()
823 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4); in sata_phy_instance_init()
824 tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK); in sata_phy_instance_init()
825 tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07); in sata_phy_instance_init()
826 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4); in sata_phy_instance_init()
828 tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4); in sata_phy_instance_init()
829 tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK); in sata_phy_instance_init()
830 tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02); in sata_phy_instance_init()
831 writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4); in sata_phy_instance_init()
833 tmp = readl(phyd + PHYD_DESIGN_OPTION2); in sata_phy_instance_init()
834 tmp &= ~RG_LOCK_CNT_SEL_MSK; in sata_phy_instance_init()
835 tmp |= RG_LOCK_CNT_SEL_VAL(0x02); in sata_phy_instance_init()
836 writel(tmp, phyd + PHYD_DESIGN_OPTION2); in sata_phy_instance_init()
838 tmp = readl(phyd + PHYD_DESIGN_OPTION9); in sata_phy_instance_init()
839 tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK | in sata_phy_instance_init()
841 tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | in sata_phy_instance_init()
843 writel(tmp, phyd + PHYD_DESIGN_OPTION9); in sata_phy_instance_init()
845 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1); in sata_phy_instance_init()
846 tmp &= ~RG_IDRV_0DB_GEN1_MSK; in sata_phy_instance_init()
847 tmp |= RG_IDRV_0DB_GEN1_VAL(0x20); in sata_phy_instance_init()
848 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1); in sata_phy_instance_init()
850 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1); in sata_phy_instance_init()
851 tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK; in sata_phy_instance_init()
852 tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03); in sata_phy_instance_init()
853 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1); in sata_phy_instance_init()
941 u32 tmp; in u2_phy_props_set() local
944 tmp = readl(com + U3P_U2PHYBC12C); in u2_phy_props_set()
945 tmp |= P2C_RG_CHGDT_EN; /* BC1.2 path Enable */ in u2_phy_props_set()
946 writel(tmp, com + U3P_U2PHYBC12C); in u2_phy_props_set()
950 tmp = readl(com + U3P_USBPHYACR5); in u2_phy_props_set()
951 tmp &= ~PA5_RG_U2_HSTX_SRCTRL; in u2_phy_props_set()
952 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src); in u2_phy_props_set()
953 writel(tmp, com + U3P_USBPHYACR5); in u2_phy_props_set()
957 tmp = readl(com + U3P_USBPHYACR1); in u2_phy_props_set()
958 tmp &= ~PA1_RG_VRT_SEL; in u2_phy_props_set()
959 tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt); in u2_phy_props_set()
960 writel(tmp, com + U3P_USBPHYACR1); in u2_phy_props_set()
964 tmp = readl(com + U3P_USBPHYACR1); in u2_phy_props_set()
965 tmp &= ~PA1_RG_TERM_SEL; in u2_phy_props_set()
966 tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term); in u2_phy_props_set()
967 writel(tmp, com + U3P_USBPHYACR1); in u2_phy_props_set()
971 tmp = readl(com + U3P_USBPHYACR1); in u2_phy_props_set()
972 tmp &= ~PA1_RG_INTR_CAL; in u2_phy_props_set()
973 tmp |= PA1_RG_INTR_CAL_VAL(instance->intr); in u2_phy_props_set()
974 writel(tmp, com + U3P_USBPHYACR1); in u2_phy_props_set()
978 tmp = readl(com + U3P_USBPHYACR6); in u2_phy_props_set()
979 tmp &= ~PA6_RG_U2_DISCTH; in u2_phy_props_set()
980 tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth); in u2_phy_props_set()
981 writel(tmp, com + U3P_USBPHYACR6); in u2_phy_props_set()