Lines Matching refs:config_reg
270 u32 config_reg; in zynqmp_qspi_init_hw() local
292 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); in zynqmp_qspi_init_hw()
293 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; in zynqmp_qspi_init_hw()
295 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK; in zynqmp_qspi_init_hw()
297 config_reg &= ~GQSPI_CFG_ENDIAN_MASK; in zynqmp_qspi_init_hw()
299 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK; in zynqmp_qspi_init_hw()
301 config_reg |= GQSPI_CFG_WP_HOLD_MASK; in zynqmp_qspi_init_hw()
303 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; in zynqmp_qspi_init_hw()
305 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; in zynqmp_qspi_init_hw()
307 config_reg &= ~GQSPI_CFG_CLK_POL_MASK; in zynqmp_qspi_init_hw()
308 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); in zynqmp_qspi_init_hw()
451 u32 config_reg, baud_rate_val = 0; in zynqmp_qspi_config_op() local
462 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); in zynqmp_qspi_config_op()
465 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK); in zynqmp_qspi_config_op()
468 config_reg |= GQSPI_CFG_CLK_PHA_MASK; in zynqmp_qspi_config_op()
470 config_reg |= GQSPI_CFG_CLK_POL_MASK; in zynqmp_qspi_config_op()
472 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; in zynqmp_qspi_config_op()
473 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT); in zynqmp_qspi_config_op()
474 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); in zynqmp_qspi_config_op()
639 u32 config_reg, genfifoentry; in zynqmp_process_dma_irq() local
653 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); in zynqmp_process_dma_irq()
654 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; in zynqmp_process_dma_irq()
655 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); in zynqmp_process_dma_irq()
738 u32 rx_bytes, rx_rem, config_reg; in zynqmp_qspi_setuprxdma() local
745 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); in zynqmp_qspi_setuprxdma()
746 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; in zynqmp_qspi_setuprxdma()
747 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); in zynqmp_qspi_setuprxdma()
772 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); in zynqmp_qspi_setuprxdma()
773 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; in zynqmp_qspi_setuprxdma()
774 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK; in zynqmp_qspi_setuprxdma()
775 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); in zynqmp_qspi_setuprxdma()
798 u32 config_reg; in zynqmp_qspi_write_op() local
803 config_reg = zynqmp_gqspi_read(xqspi, in zynqmp_qspi_write_op()
805 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; in zynqmp_qspi_write_op()
807 config_reg); in zynqmp_qspi_write_op()