Lines Matching refs:ch
52 static void cls_set_cts_flow_control(struct jsm_channel *ch) in cls_set_cts_flow_control() argument
54 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
55 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
62 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
64 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
70 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
73 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
81 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
84 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
88 &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
90 ch->ch_t_tlevel = 16; in cls_set_cts_flow_control()
93 static void cls_set_ixon_flow_control(struct jsm_channel *ch) in cls_set_ixon_flow_control() argument
95 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
96 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
103 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
105 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
111 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
114 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixon_flow_control()
115 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixon_flow_control()
116 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixon_flow_control()
117 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixon_flow_control()
120 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
128 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
131 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
135 &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
138 static void cls_set_no_output_flow_control(struct jsm_channel *ch) in cls_set_no_output_flow_control() argument
140 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
141 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
148 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
150 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
156 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
159 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
167 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
170 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
174 &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
176 ch->ch_r_watermark = 0; in cls_set_no_output_flow_control()
177 ch->ch_t_tlevel = 16; in cls_set_no_output_flow_control()
178 ch->ch_r_tlevel = 16; in cls_set_no_output_flow_control()
181 static void cls_set_rts_flow_control(struct jsm_channel *ch) in cls_set_rts_flow_control() argument
183 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
184 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
191 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
193 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
199 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
202 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
206 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
209 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
213 &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
215 ch->ch_r_watermark = 4; in cls_set_rts_flow_control()
216 ch->ch_r_tlevel = 8; in cls_set_rts_flow_control()
219 static void cls_set_ixoff_flow_control(struct jsm_channel *ch) in cls_set_ixoff_flow_control() argument
221 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
222 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
229 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
231 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
237 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
240 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixoff_flow_control()
241 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixoff_flow_control()
242 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixoff_flow_control()
243 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixoff_flow_control()
246 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
250 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
253 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
257 &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
260 static void cls_set_no_input_flow_control(struct jsm_channel *ch) in cls_set_no_input_flow_control() argument
262 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
263 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
270 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
272 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
278 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
281 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
285 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
288 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
292 &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
294 ch->ch_t_tlevel = 16; in cls_set_no_input_flow_control()
295 ch->ch_r_tlevel = 16; in cls_set_no_input_flow_control()
305 static void cls_clear_break(struct jsm_channel *ch) in cls_clear_break() argument
309 spin_lock_irqsave(&ch->ch_lock, lock_flags); in cls_clear_break()
312 if (ch->ch_flags & CH_BREAK_SENDING) { in cls_clear_break()
313 u8 temp = readb(&ch->ch_cls_uart->lcr); in cls_clear_break()
315 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_clear_break()
317 ch->ch_flags &= ~(CH_BREAK_SENDING); in cls_clear_break()
318 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in cls_clear_break()
322 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in cls_clear_break()
325 static void cls_disable_receiver(struct jsm_channel *ch) in cls_disable_receiver() argument
327 u8 tmp = readb(&ch->ch_cls_uart->ier); in cls_disable_receiver()
330 writeb(tmp, &ch->ch_cls_uart->ier); in cls_disable_receiver()
333 static void cls_enable_receiver(struct jsm_channel *ch) in cls_enable_receiver() argument
335 u8 tmp = readb(&ch->ch_cls_uart->ier); in cls_enable_receiver()
338 writeb(tmp, &ch->ch_cls_uart->ier); in cls_enable_receiver()
342 static void cls_assert_modem_signals(struct jsm_channel *ch) in cls_assert_modem_signals() argument
344 if (!ch) in cls_assert_modem_signals()
347 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr); in cls_assert_modem_signals()
350 static void cls_copy_data_from_uart_to_queue(struct jsm_channel *ch) in cls_copy_data_from_uart_to_queue() argument
359 if (!ch) in cls_copy_data_from_uart_to_queue()
362 spin_lock_irqsave(&ch->ch_lock, flags); in cls_copy_data_from_uart_to_queue()
365 head = ch->ch_r_head & RQUEUEMASK; in cls_copy_data_from_uart_to_queue()
366 tail = ch->ch_r_tail & RQUEUEMASK; in cls_copy_data_from_uart_to_queue()
369 linestatus = ch->ch_cached_lsr; in cls_copy_data_from_uart_to_queue()
370 ch->ch_cached_lsr = 0; in cls_copy_data_from_uart_to_queue()
381 if (ch->ch_c_iflag & IGNBRK) in cls_copy_data_from_uart_to_queue()
389 linestatus = readb(&ch->ch_cls_uart->lsr); in cls_copy_data_from_uart_to_queue()
401 readb(&ch->ch_cls_uart->txrx); in cls_copy_data_from_uart_to_queue()
415 ch->ch_r_tail = tail; in cls_copy_data_from_uart_to_queue()
416 ch->ch_err_overrun++; in cls_copy_data_from_uart_to_queue()
420 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE in cls_copy_data_from_uart_to_queue()
422 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx); in cls_copy_data_from_uart_to_queue()
426 if (ch->ch_equeue[head] & UART_LSR_PE) in cls_copy_data_from_uart_to_queue()
427 ch->ch_err_parity++; in cls_copy_data_from_uart_to_queue()
428 if (ch->ch_equeue[head] & UART_LSR_BI) in cls_copy_data_from_uart_to_queue()
429 ch->ch_err_break++; in cls_copy_data_from_uart_to_queue()
430 if (ch->ch_equeue[head] & UART_LSR_FE) in cls_copy_data_from_uart_to_queue()
431 ch->ch_err_frame++; in cls_copy_data_from_uart_to_queue()
435 ch->ch_rxcount++; in cls_copy_data_from_uart_to_queue()
441 ch->ch_r_head = head & RQUEUEMASK; in cls_copy_data_from_uart_to_queue()
442 ch->ch_e_head = head & EQUEUEMASK; in cls_copy_data_from_uart_to_queue()
444 spin_unlock_irqrestore(&ch->ch_lock, flags); in cls_copy_data_from_uart_to_queue()
447 static void cls_copy_data_from_queue_to_uart(struct jsm_channel *ch) in cls_copy_data_from_queue_to_uart() argument
455 if (!ch) in cls_copy_data_from_queue_to_uart()
458 circ = &ch->uart_port.state->xmit; in cls_copy_data_from_queue_to_uart()
465 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) in cls_copy_data_from_queue_to_uart()
469 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) in cls_copy_data_from_queue_to_uart()
482 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx); in cls_copy_data_from_queue_to_uart()
485 ch->ch_txcount++; in cls_copy_data_from_queue_to_uart()
492 if (len_written > ch->ch_t_tlevel) in cls_copy_data_from_queue_to_uart()
493 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_copy_data_from_queue_to_uart()
496 uart_write_wakeup(&ch->uart_port); in cls_copy_data_from_queue_to_uart()
499 static void cls_parse_modem(struct jsm_channel *ch, u8 signals) in cls_parse_modem() argument
503 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in cls_parse_modem()
505 ch->ch_portnum, msignals); in cls_parse_modem()
515 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); in cls_parse_modem()
517 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS); in cls_parse_modem()
520 ch->ch_mistat |= UART_MSR_DCD; in cls_parse_modem()
522 ch->ch_mistat &= ~UART_MSR_DCD; in cls_parse_modem()
525 ch->ch_mistat |= UART_MSR_DSR; in cls_parse_modem()
527 ch->ch_mistat &= ~UART_MSR_DSR; in cls_parse_modem()
530 ch->ch_mistat |= UART_MSR_RI; in cls_parse_modem()
532 ch->ch_mistat &= ~UART_MSR_RI; in cls_parse_modem()
535 ch->ch_mistat |= UART_MSR_CTS; in cls_parse_modem()
537 ch->ch_mistat &= ~UART_MSR_CTS; in cls_parse_modem()
539 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in cls_parse_modem()
541 ch->ch_portnum, in cls_parse_modem()
542 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), in cls_parse_modem()
543 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), in cls_parse_modem()
544 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), in cls_parse_modem()
545 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), in cls_parse_modem()
546 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), in cls_parse_modem()
547 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); in cls_parse_modem()
553 struct jsm_channel *ch; in cls_parse_isr() local
565 ch = brd->channels[port]; in cls_parse_isr()
566 if (!ch) in cls_parse_isr()
571 isr = readb(&ch->ch_cls_uart->isr_fcr); in cls_parse_isr()
580 cls_copy_data_from_uart_to_queue(ch); in cls_parse_isr()
581 jsm_check_queue_flow_control(ch); in cls_parse_isr()
587 spin_lock_irqsave(&ch->ch_lock, flags); in cls_parse_isr()
588 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_parse_isr()
589 spin_unlock_irqrestore(&ch->ch_lock, flags); in cls_parse_isr()
590 cls_copy_data_from_queue_to_uart(ch); in cls_parse_isr()
600 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); in cls_parse_isr()
605 static void cls_flush_uart_write(struct jsm_channel *ch) in cls_flush_uart_write() argument
610 if (!ch) in cls_flush_uart_write()
614 &ch->ch_cls_uart->isr_fcr); in cls_flush_uart_write()
618 tmp = readb(&ch->ch_cls_uart->isr_fcr); in cls_flush_uart_write()
620 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in cls_flush_uart_write()
627 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_flush_uart_write()
631 static void cls_flush_uart_read(struct jsm_channel *ch) in cls_flush_uart_read() argument
633 if (!ch) in cls_flush_uart_read()
650 static void cls_send_start_character(struct jsm_channel *ch) in cls_send_start_character() argument
652 if (!ch) in cls_send_start_character()
655 if (ch->ch_startc != __DISABLED_CHAR) { in cls_send_start_character()
656 ch->ch_xon_sends++; in cls_send_start_character()
657 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx); in cls_send_start_character()
661 static void cls_send_stop_character(struct jsm_channel *ch) in cls_send_stop_character() argument
663 if (!ch) in cls_send_stop_character()
666 if (ch->ch_stopc != __DISABLED_CHAR) { in cls_send_stop_character()
667 ch->ch_xoff_sends++; in cls_send_stop_character()
668 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx); in cls_send_stop_character()
676 static void cls_param(struct jsm_channel *ch) in cls_param() argument
687 bd = ch->ch_bd; in cls_param()
694 if ((ch->ch_c_cflag & (CBAUD)) == 0) { in cls_param()
695 ch->ch_r_head = 0; in cls_param()
696 ch->ch_r_tail = 0; in cls_param()
697 ch->ch_e_head = 0; in cls_param()
698 ch->ch_e_tail = 0; in cls_param()
700 cls_flush_uart_write(ch); in cls_param()
701 cls_flush_uart_read(ch); in cls_param()
704 ch->ch_flags |= (CH_BAUD0); in cls_param()
705 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); in cls_param()
706 cls_assert_modem_signals(ch); in cls_param()
710 cflag = C_BAUD(ch->uart_port.state->port.tty); in cls_param()
719 if (ch->ch_flags & CH_BAUD0) in cls_param()
720 ch->ch_flags &= ~(CH_BAUD0); in cls_param()
722 if (ch->ch_c_cflag & PARENB) in cls_param()
725 if (!(ch->ch_c_cflag & PARODD)) in cls_param()
733 if (ch->ch_c_cflag & CMSPAR) in cls_param()
737 if (ch->ch_c_cflag & CSTOPB) in cls_param()
740 switch (ch->ch_c_cflag & CSIZE) { in cls_param()
756 ier = readb(&ch->ch_cls_uart->ier); in cls_param()
757 uart_lcr = readb(&ch->ch_cls_uart->lcr); in cls_param()
759 quot = ch->ch_bd->bd_dividend / baud; in cls_param()
762 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr); in cls_param()
763 writeb((quot & 0xff), &ch->ch_cls_uart->txrx); in cls_param()
764 writeb((quot >> 8), &ch->ch_cls_uart->ier); in cls_param()
765 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
769 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
771 if (ch->ch_c_cflag & CREAD) in cls_param()
776 writeb(ier, &ch->ch_cls_uart->ier); in cls_param()
778 if (ch->ch_c_cflag & CRTSCTS) in cls_param()
779 cls_set_cts_flow_control(ch); in cls_param()
780 else if (ch->ch_c_iflag & IXON) { in cls_param()
785 if ((ch->ch_startc == __DISABLED_CHAR) || in cls_param()
786 (ch->ch_stopc == __DISABLED_CHAR)) in cls_param()
787 cls_set_no_output_flow_control(ch); in cls_param()
789 cls_set_ixon_flow_control(ch); in cls_param()
791 cls_set_no_output_flow_control(ch); in cls_param()
793 if (ch->ch_c_cflag & CRTSCTS) in cls_param()
794 cls_set_rts_flow_control(ch); in cls_param()
795 else if (ch->ch_c_iflag & IXOFF) { in cls_param()
800 if ((ch->ch_startc == __DISABLED_CHAR) || in cls_param()
801 (ch->ch_stopc == __DISABLED_CHAR)) in cls_param()
802 cls_set_no_input_flow_control(ch); in cls_param()
804 cls_set_ixoff_flow_control(ch); in cls_param()
806 cls_set_no_input_flow_control(ch); in cls_param()
808 cls_assert_modem_signals(ch); in cls_param()
811 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); in cls_param()
857 static void cls_uart_init(struct jsm_channel *ch) in cls_uart_init() argument
859 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); in cls_uart_init()
862 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_init()
868 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_uart_init()
870 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_uart_init()
875 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
878 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_uart_init()
881 readb(&ch->ch_cls_uart->txrx); in cls_uart_init()
884 &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
887 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_uart_init()
889 readb(&ch->ch_cls_uart->lsr); in cls_uart_init()
890 readb(&ch->ch_cls_uart->msr); in cls_uart_init()
896 static void cls_uart_off(struct jsm_channel *ch) in cls_uart_off() argument
899 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_off()
908 static u32 cls_get_uart_bytes_left(struct jsm_channel *ch) in cls_get_uart_bytes_left() argument
911 u8 lsr = readb(&ch->ch_cls_uart->lsr); in cls_get_uart_bytes_left()
917 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_get_uart_bytes_left()
930 static void cls_send_break(struct jsm_channel *ch) in cls_send_break() argument
933 if (!(ch->ch_flags & CH_BREAK_SENDING)) { in cls_send_break()
934 u8 temp = readb(&ch->ch_cls_uart->lcr); in cls_send_break()
936 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_send_break()
937 ch->ch_flags |= (CH_BREAK_SENDING); in cls_send_break()
948 static void cls_send_immediate_char(struct jsm_channel *ch, unsigned char c) in cls_send_immediate_char() argument
950 writeb(c, &ch->ch_cls_uart->txrx); in cls_send_immediate_char()