Lines Matching refs:temp
258 u16 temp; in xhci_common_hub_descriptor() local
263 temp = 0; in xhci_common_hub_descriptor()
266 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
268 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
271 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
274 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
282 u16 temp; in xhci_usb2_hub_descriptor() local
292 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
293 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
661 u32 temp; in xhci_set_port_power() local
665 temp = readl(port->addr); in xhci_set_port_power()
668 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); in xhci_set_port_power()
670 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
674 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
678 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
682 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
684 if (temp) in xhci_set_port_power()
693 u32 temp; in xhci_port_set_test_mode() local
698 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
699 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
700 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
771 u32 temp; in xhci_set_link_state() local
775 temp = xhci_port_state_to_neutral(portsc); in xhci_set_link_state()
776 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
777 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
778 writel(temp, port->addr); in xhci_set_link_state()
782 portsc, temp); in xhci_set_link_state()
788 u32 temp; in xhci_set_remote_wake_mask() local
790 temp = readl(port->addr); in xhci_set_remote_wake_mask()
791 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
794 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
796 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
799 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
801 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
804 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
806 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
808 writel(temp, port->addr); in xhci_set_remote_wake_mask()
815 u32 temp; in xhci_test_and_clear_bit() local
817 temp = readl(port->addr); in xhci_test_and_clear_bit()
818 if (temp & port_bit) { in xhci_test_and_clear_bit()
819 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
820 temp |= port_bit; in xhci_test_and_clear_bit()
821 writel(temp, port->addr); in xhci_test_and_clear_bit()
1184 u32 temp, status; in xhci_hub_control() local
1235 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1236 if (temp == ~(u32)0) { in xhci_hub_control()
1241 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1242 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1248 hcd->self.busnum, wIndex + 1, temp, status); in xhci_hub_control()
1261 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1278 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1279 if (temp == ~(u32)0) { in xhci_hub_control()
1284 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1288 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1289 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1301 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1302 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1303 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1326 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1330 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1335 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1340 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1343 writel(temp | PORT_PE, ports[wIndex]->addr); in xhci_hub_control()
1344 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1354 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1378 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1388 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1392 if (!(temp & PORT_PE)) { in xhci_hub_control()
1412 u32 pls = temp & PORT_PLS_MASK; in xhci_hub_control()
1438 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1458 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1459 if ((temp & PORT_PLS_MASK) == XDEV_U3) in xhci_hub_control()
1463 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1477 temp = (temp | PORT_RESET); in xhci_hub_control()
1478 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1480 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1482 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1487 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1489 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1492 temp |= PORT_WR; in xhci_hub_control()
1493 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1494 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1499 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1500 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1501 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1502 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1507 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1508 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1509 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1510 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1526 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1532 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1533 if (temp == ~(u32)0) { in xhci_hub_control()
1539 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1542 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1544 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1545 if (temp & PORT_RESET) in xhci_hub_control()
1547 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1548 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1584 ports[wIndex]->addr, temp); in xhci_hub_control()
1588 ports[wIndex]->addr, temp); in xhci_hub_control()
1620 u32 temp, status; in xhci_hub_status_data() local
1651 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1652 if (temp == ~(u32)0) { in xhci_hub_status_data()
1657 trace_xhci_hub_status_data(i, temp); in xhci_hub_status_data()
1659 if ((temp & mask) != 0 || in xhci_hub_status_data()
1666 if ((temp & PORT_RC)) in xhci_hub_status_data()
1668 if (temp & PORT_OC) in xhci_hub_status_data()
1850 u32 temp, portsc; in xhci_bus_resume() local
1869 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1870 temp &= ~CMD_EIE; in xhci_bus_resume()
1871 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1948 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1949 temp |= CMD_EIE; in xhci_bus_resume()
1950 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1951 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()