Lines Matching refs:wIndex
568 u16 wIndex, __le32 __iomem *addr, u32 port_status) in xhci_disable_port() argument
587 hcd->self.busnum, wIndex + 1, port_status); in xhci_disable_port()
591 u16 wIndex, __le32 __iomem *addr, u32 port_status) in xhci_clear_port_change_bit() argument
638 wIndex + 1, port_change_bit, port_status); in xhci_clear_port_change_bit()
691 u16 test_mode, u16 wIndex) in xhci_port_set_test_mode() argument
697 port = xhci->usb2_rhub.ports[wIndex]; in xhci_port_set_test_mode()
707 u16 test_mode, u16 wIndex, unsigned long *flags) in xhci_enter_test_mode() argument
744 test_mode, wIndex + 1); in xhci_enter_test_mode()
745 xhci_port_set_test_mode(xhci, test_mode, wIndex); in xhci_enter_test_mode()
887 u16 wIndex) in xhci_del_comp_mod_timer() argument
896 xhci->port_status_u0 |= 1 << wIndex; in xhci_del_comp_mod_timer()
915 u32 wIndex; in xhci_handle_usb2_port_link_resume() local
920 wIndex = port->hcd_portnum; in xhci_handle_usb2_port_link_resume()
927 if (!bus_state->resume_done[wIndex]) { in xhci_handle_usb2_port_link_resume()
929 if (test_bit(wIndex, &bus_state->resuming_ports)) { in xhci_handle_usb2_port_link_resume()
943 set_bit(wIndex, &bus_state->resuming_ports); in xhci_handle_usb2_port_link_resume()
944 bus_state->resume_done[wIndex] = timeout; in xhci_handle_usb2_port_link_resume()
946 usb_hcd_start_port_resume(&hcd->self, wIndex); in xhci_handle_usb2_port_link_resume()
949 } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) { in xhci_handle_usb2_port_link_resume()
953 hcd->self.busnum, wIndex + 1); in xhci_handle_usb2_port_link_resume()
955 bus_state->resume_done[wIndex] = 0; in xhci_handle_usb2_port_link_resume()
956 clear_bit(wIndex, &bus_state->resuming_ports); in xhci_handle_usb2_port_link_resume()
958 set_bit(wIndex, &bus_state->rexit_ports); in xhci_handle_usb2_port_link_resume()
965 &bus_state->rexit_done[wIndex], in xhci_handle_usb2_port_link_resume()
971 wIndex + 1); in xhci_handle_usb2_port_link_resume()
982 hcd->self.busnum, wIndex + 1, port_status); in xhci_handle_usb2_port_link_resume()
984 clear_bit(wIndex, &bus_state->rexit_ports); in xhci_handle_usb2_port_link_resume()
987 usb_hcd_end_port_resume(&hcd->self, wIndex); in xhci_handle_usb2_port_link_resume()
988 bus_state->port_c_suspend |= 1 << wIndex; in xhci_handle_usb2_port_link_resume()
989 bus_state->suspended_ports &= ~(1 << wIndex); in xhci_handle_usb2_port_link_resume()
1119 u16 wIndex, u32 raw_port_status, in xhci_get_port_status() argument
1129 port = rhub->ports[wIndex]; in xhci_get_port_status()
1163 if ((bus_state->resume_done[wIndex] || in xhci_get_port_status()
1164 test_bit(wIndex, &bus_state->resuming_ports)) && in xhci_get_port_status()
1167 bus_state->resume_done[wIndex] = 0; in xhci_get_port_status()
1168 clear_bit(wIndex, &bus_state->resuming_ports); in xhci_get_port_status()
1169 usb_hcd_end_port_resume(&hcd->self, wIndex); in xhci_get_port_status()
1172 if (bus_state->port_c_suspend & (1 << wIndex)) in xhci_get_port_status()
1179 u16 wIndex, char *buf, u16 wLength) in xhci_hub_control() argument
1232 if (!wIndex || wIndex > max_ports) in xhci_hub_control()
1234 wIndex--; in xhci_hub_control()
1235 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1241 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1242 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1248 hcd->self.busnum, wIndex + 1, temp, status); in xhci_hub_control()
1260 port_li = readl(ports[wIndex]->addr + PORTLI); in xhci_hub_control()
1267 link_state = (wIndex & 0xff00) >> 3; in xhci_hub_control()
1269 wake_mask = wIndex & 0xff00; in xhci_hub_control()
1271 test_mode = (wIndex & 0xff00) >> 8; in xhci_hub_control()
1273 timeout = (wIndex & 0xff00) >> 8; in xhci_hub_control()
1274 wIndex &= 0xff; in xhci_hub_control()
1275 if (!wIndex || wIndex > max_ports) in xhci_hub_control()
1277 wIndex--; in xhci_hub_control()
1278 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1288 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1291 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1301 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1305 hcd->self.busnum, wIndex + 1); in xhci_hub_control()
1310 wIndex + 1); in xhci_hub_control()
1320 xhci_set_link_state(xhci, ports[wIndex], XDEV_U3); in xhci_hub_control()
1326 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1327 bus_state->suspended_ports |= 1 << wIndex; in xhci_hub_control()
1330 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1334 hcd->self.busnum, wIndex + 1); in xhci_hub_control()
1343 writel(temp | PORT_PE, ports[wIndex]->addr); in xhci_hub_control()
1344 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1351 hcd->self.busnum, wIndex + 1); in xhci_hub_control()
1352 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1354 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1384 hcd->self.busnum, wIndex + 1); in xhci_hub_control()
1385 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1388 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1399 hcd->self.busnum, wIndex + 1, in xhci_hub_control()
1422 reinit_completion(&bus_state->u3exit_done[wIndex]); in xhci_hub_control()
1425 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1433 if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex], in xhci_hub_control()
1436 hcd->self.busnum, wIndex + 1); in xhci_hub_control()
1438 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1445 wIndex + 1); in xhci_hub_control()
1454 xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3); in xhci_hub_control()
1458 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1463 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1464 bus_state->suspended_ports |= 1 << wIndex; in xhci_hub_control()
1474 xhci_set_port_power(xhci, hcd, wIndex, true, &flags); in xhci_hub_control()
1478 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1480 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1482 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1485 xhci_set_remote_wake_mask(xhci, ports[wIndex], in xhci_hub_control()
1487 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1489 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1493 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1494 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1499 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1502 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1507 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1510 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1519 retval = xhci_enter_test_mode(xhci, test_mode, wIndex, in xhci_hub_control()
1526 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1529 if (!wIndex || wIndex > max_ports) in xhci_hub_control()
1531 wIndex--; in xhci_hub_control()
1532 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1542 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1551 set_bit(wIndex, &bus_state->resuming_ports); in xhci_hub_control()
1552 usb_hcd_start_port_resume(&hcd->self, wIndex); in xhci_hub_control()
1553 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1558 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1560 clear_bit(wIndex, &bus_state->resuming_ports); in xhci_hub_control()
1561 usb_hcd_end_port_resume(&hcd->self, wIndex); in xhci_hub_control()
1563 bus_state->port_c_suspend |= 1 << wIndex; in xhci_hub_control()
1566 wIndex + 1); in xhci_hub_control()
1574 bus_state->port_c_suspend &= ~(1 << wIndex); in xhci_hub_control()
1583 xhci_clear_port_change_bit(xhci, wValue, wIndex, in xhci_hub_control()
1584 ports[wIndex]->addr, temp); in xhci_hub_control()
1587 xhci_disable_port(hcd, xhci, wIndex, in xhci_hub_control()
1588 ports[wIndex]->addr, temp); in xhci_hub_control()
1591 xhci_set_port_power(xhci, hcd, wIndex, false, &flags); in xhci_hub_control()