Lines Matching refs:tmp
132 u32 tmp; in radeon_pm_disable_dynamic_mode() local
137 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
138 tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK; in radeon_pm_disable_dynamic_mode()
139 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK; in radeon_pm_disable_dynamic_mode()
140 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
142 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
143 tmp |= (MCLK_CNTL__FORCE_MCLKA | in radeon_pm_disable_dynamic_mode()
149 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
154 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
155 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP | in radeon_pm_disable_dynamic_mode()
162 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
168 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_disable_dynamic_mode()
169 tmp |= (SCLK_CNTL2__R300_FORCE_TCL | in radeon_pm_disable_dynamic_mode()
172 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_disable_dynamic_mode()
174 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
175 tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP | in radeon_pm_disable_dynamic_mode()
183 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
185 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_disable_dynamic_mode()
186 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI | in radeon_pm_disable_dynamic_mode()
188 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
190 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
191 tmp |= (MCLK_CNTL__FORCE_MCLKA | in radeon_pm_disable_dynamic_mode()
196 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
198 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_disable_dynamic_mode()
199 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | in radeon_pm_disable_dynamic_mode()
202 OUTPLL(pllVCLK_ECP_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
204 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_disable_dynamic_mode()
205 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | in radeon_pm_disable_dynamic_mode()
218 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
226 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_disable_dynamic_mode()
227 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2); in radeon_pm_disable_dynamic_mode()
233 tmp |= SCLK_CNTL__FORCE_HDP| in radeon_pm_disable_dynamic_mode()
251 tmp |= SCLK_CNTL__FORCE_HDP | in radeon_pm_disable_dynamic_mode()
258 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
262 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_disable_dynamic_mode()
263 tmp |= SCLK_CNTL2__R300_FORCE_TCL | in radeon_pm_disable_dynamic_mode()
266 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_disable_dynamic_mode()
270 tmp = INPLL(pllCLK_PIN_CNTL); in radeon_pm_disable_dynamic_mode()
271 tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL; in radeon_pm_disable_dynamic_mode()
272 OUTPLL(pllCLK_PIN_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
279 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
280 tmp &= ~(MCLK_CNTL__FORCE_MCLKA | in radeon_pm_disable_dynamic_mode()
282 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
287 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_disable_dynamic_mode()
288 tmp |= (MCLK_CNTL__FORCE_MCLKA | in radeon_pm_disable_dynamic_mode()
292 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
295 tmp = INPLL(pllMCLK_MISC); in radeon_pm_disable_dynamic_mode()
296 tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT| in radeon_pm_disable_dynamic_mode()
300 OUTPLL(pllMCLK_MISC, tmp); in radeon_pm_disable_dynamic_mode()
305 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_disable_dynamic_mode()
306 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS| in radeon_pm_disable_dynamic_mode()
309 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
313 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_disable_dynamic_mode()
314 tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | in radeon_pm_disable_dynamic_mode()
321 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
324 tmp = INPLL( pllVCLK_ECP_CNTL); in radeon_pm_disable_dynamic_mode()
325 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | in radeon_pm_disable_dynamic_mode()
327 OUTPLL( pllVCLK_ECP_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
333 u32 tmp; in radeon_pm_enable_dynamic_mode() local
337 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
340 tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB); in radeon_pm_enable_dynamic_mode()
341 tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 | in radeon_pm_enable_dynamic_mode()
346 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
352 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_enable_dynamic_mode()
353 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL | in radeon_pm_enable_dynamic_mode()
356 tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT | in radeon_pm_enable_dynamic_mode()
359 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_enable_dynamic_mode()
361 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
362 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP | in radeon_pm_enable_dynamic_mode()
370 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK; in radeon_pm_enable_dynamic_mode()
371 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
373 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_enable_dynamic_mode()
374 tmp &= ~SCLK_MORE_CNTL__FORCEON; in radeon_pm_enable_dynamic_mode()
375 tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT | in radeon_pm_enable_dynamic_mode()
378 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
380 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_enable_dynamic_mode()
381 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | in radeon_pm_enable_dynamic_mode()
383 OUTPLL(pllVCLK_ECP_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
385 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_enable_dynamic_mode()
386 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | in radeon_pm_enable_dynamic_mode()
399 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
401 tmp = INPLL(pllMCLK_MISC); in radeon_pm_enable_dynamic_mode()
402 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE | in radeon_pm_enable_dynamic_mode()
404 OUTPLL(pllMCLK_MISC, tmp); in radeon_pm_enable_dynamic_mode()
406 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
407 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB); in radeon_pm_enable_dynamic_mode()
408 tmp &= ~(MCLK_CNTL__FORCE_YCLKA | in radeon_pm_enable_dynamic_mode()
417 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) && in radeon_pm_enable_dynamic_mode()
418 (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) { in radeon_pm_enable_dynamic_mode()
420 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
423 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB; in radeon_pm_enable_dynamic_mode()
425 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA; in radeon_pm_enable_dynamic_mode()
427 tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA | in radeon_pm_enable_dynamic_mode()
431 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
437 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
438 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP); in radeon_pm_enable_dynamic_mode()
439 tmp |= SCLK_CNTL__FORCE_CP; in radeon_pm_enable_dynamic_mode()
440 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
443 tmp = INPLL(pllSCLK_CNTL2); in radeon_pm_enable_dynamic_mode()
444 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL | in radeon_pm_enable_dynamic_mode()
447 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_enable_dynamic_mode()
452 tmp = INPLL( pllCLK_PWRMGT_CNTL); in radeon_pm_enable_dynamic_mode()
453 tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK| in radeon_pm_enable_dynamic_mode()
456 tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK | in radeon_pm_enable_dynamic_mode()
458 OUTPLL( pllCLK_PWRMGT_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
461 tmp = INPLL(pllCLK_PIN_CNTL); in radeon_pm_enable_dynamic_mode()
462 tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL; in radeon_pm_enable_dynamic_mode()
463 OUTPLL(pllCLK_PIN_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
469 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_enable_dynamic_mode()
470 tmp &= ~SCLK_CNTL__FORCEON_MASK; in radeon_pm_enable_dynamic_mode()
477 tmp |= SCLK_CNTL__FORCE_CP; in radeon_pm_enable_dynamic_mode()
478 tmp |= SCLK_CNTL__FORCE_VIP; in radeon_pm_enable_dynamic_mode()
480 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
486 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_pm_enable_dynamic_mode()
487 tmp &= ~SCLK_MORE_CNTL__FORCEON; in radeon_pm_enable_dynamic_mode()
493 tmp |= SCLK_MORE_CNTL__FORCEON; in radeon_pm_enable_dynamic_mode()
495 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
504 tmp = INPLL(pllPLL_PWRMGT_CNTL); in radeon_pm_enable_dynamic_mode()
505 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE; in radeon_pm_enable_dynamic_mode()
506 OUTPLL(pllPLL_PWRMGT_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
510 tmp = INPLL(pllPIXCLKS_CNTL); in radeon_pm_enable_dynamic_mode()
511 tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | in radeon_pm_enable_dynamic_mode()
518 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
521 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_enable_dynamic_mode()
522 tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | in radeon_pm_enable_dynamic_mode()
524 OUTPLL(pllVCLK_ECP_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
529 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_enable_dynamic_mode()
530 tmp &= ~(MCLK_CNTL__FORCE_MCLKA | in radeon_pm_enable_dynamic_mode()
534 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
537 tmp = INPLL(pllMCLK_MISC); in radeon_pm_enable_dynamic_mode()
538 tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT| in radeon_pm_enable_dynamic_mode()
542 OUTPLL(pllMCLK_MISC, tmp); in radeon_pm_enable_dynamic_mode()
834 u32 tmp; in radeon_pm_setup_for_suspend() local
952 tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND; in radeon_pm_setup_for_suspend()
953 OUTPLL( pllMCLK_MISC, tmp); in radeon_pm_setup_for_suspend()
989 tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL; in radeon_pm_setup_for_suspend()
990 OUTPLL( pllPLL_PWRMGT_CNTL, tmp); in radeon_pm_setup_for_suspend()
1437 u32 tmp, tmp2; in radeon_pm_reset_pad_ctlr_strength() local
1443 tmp = INREG(PAD_CTLR_STRENGTH); in radeon_pm_reset_pad_ctlr_strength()
1447 if (tmp != tmp2) { in radeon_pm_reset_pad_ctlr_strength()
1448 tmp = tmp2; in radeon_pm_reset_pad_ctlr_strength()
1462 u32 tmp; in radeon_pm_all_ppls_off() local
1464 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_all_ppls_off()
1465 OUTPLL(pllPPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1466 tmp = INPLL(pllP2PLL_CNTL); in radeon_pm_all_ppls_off()
1467 OUTPLL(pllP2PLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1468 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_all_ppls_off()
1469 OUTPLL(pllSPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1470 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_all_ppls_off()
1471 OUTPLL(pllMPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1476 u32 tmp; in radeon_pm_start_mclk_sclk() local
1479 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_start_mclk_sclk()
1480 OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK); in radeon_pm_start_mclk_sclk()
1483 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1486 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); in radeon_pm_start_mclk_sclk()
1490 tmp = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_start_mclk_sclk()
1491 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul); in radeon_pm_start_mclk_sclk()
1492 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); in radeon_pm_start_mclk_sclk()
1495 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1496 OUTPLL(pllSPLL_CNTL, tmp & ~1); in radeon_pm_start_mclk_sclk()
1502 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1503 OUTPLL(pllSPLL_CNTL, tmp & ~0x2); in radeon_pm_start_mclk_sclk()
1509 tmp = INPLL(pllSCLK_CNTL); in radeon_pm_start_mclk_sclk()
1510 tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK; in radeon_pm_start_mclk_sclk()
1511 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK; in radeon_pm_start_mclk_sclk()
1512 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_start_mclk_sclk()
1518 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1521 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); in radeon_pm_start_mclk_sclk()
1525 tmp = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_start_mclk_sclk()
1526 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul); in radeon_pm_start_mclk_sclk()
1528 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); in radeon_pm_start_mclk_sclk()
1530 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1531 OUTPLL(pllMPLL_CNTL, tmp & ~0x2); in radeon_pm_start_mclk_sclk()
1537 tmp = INPLL(pllMPLL_CNTL); in radeon_pm_start_mclk_sclk()
1538 OUTPLL(pllMPLL_CNTL, tmp & ~0x1); in radeon_pm_start_mclk_sclk()
1544 tmp = INPLL(pllMCLK_CNTL); in radeon_pm_start_mclk_sclk()
1545 tmp |= rinfo->save_regs[2] & 0xffff; in radeon_pm_start_mclk_sclk()
1546 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_start_mclk_sclk()
1583 u32 r2ec, tmp; in radeon_pm_m10_enable_lvds_spread_spectrum() local
1599 tmp = INPLL(pllSSPLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1600 OUTPLL(pllSSPLL_CNTL, tmp & ~0x2); in radeon_pm_m10_enable_lvds_spread_spectrum()
1602 tmp = INPLL(pllSSPLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1603 OUTPLL(pllSSPLL_CNTL, tmp & ~0x1); in radeon_pm_m10_enable_lvds_spread_spectrum()
1613 tmp = INREG(LVDS_GEN_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1614 OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN); in radeon_pm_m10_enable_lvds_spread_spectrum()
1617 tmp = INREG(LVDS_PLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1618 tmp &= ~0x30000; in radeon_pm_m10_enable_lvds_spread_spectrum()
1619 tmp |= 0x10000; in radeon_pm_m10_enable_lvds_spread_spectrum()
1620 OUTREG(LVDS_PLL_CNTL, tmp); in radeon_pm_m10_enable_lvds_spread_spectrum()
1631 tmp = INPLL(pllSS_TST_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1632 tmp |= 0x00400000; in radeon_pm_m10_enable_lvds_spread_spectrum()
1633 OUTPLL(pllSS_TST_CNTL, tmp); in radeon_pm_m10_enable_lvds_spread_spectrum()
1638 u32 tmp; in radeon_pm_restore_pixel_pll() local
1645 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1646 OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80); in radeon_pm_restore_pixel_pll()
1649 tmp = INPLL(pllPPLL_REF_DIV); in radeon_pm_restore_pixel_pll()
1650 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; in radeon_pm_restore_pixel_pll()
1651 OUTPLL(pllPPLL_REF_DIV, tmp); in radeon_pm_restore_pixel_pll()
1657 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1660 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); in radeon_pm_restore_pixel_pll()
1668 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1669 OUTPLL(pllPPLL_CNTL, tmp & ~0x2); in radeon_pm_restore_pixel_pll()
1672 tmp = INPLL(pllPPLL_CNTL); in radeon_pm_restore_pixel_pll()
1673 OUTPLL(pllPPLL_CNTL, tmp & ~0x1); in radeon_pm_restore_pixel_pll()
1676 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1677 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); in radeon_pm_restore_pixel_pll()
1680 tmp = INPLL(pllVCLK_ECP_CNTL); in radeon_pm_restore_pixel_pll()
1681 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); in radeon_pm_restore_pixel_pll()
1725 u32 tmp, i; in radeon_reinitialize_M10() local
1762 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; in radeon_reinitialize_M10()
1763 tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT; in radeon_reinitialize_M10()
1764 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M10()
1766 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; in radeon_reinitialize_M10()
1767 tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT; in radeon_reinitialize_M10()
1768 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M10()
1776 tmp = rinfo->save_regs[1] in radeon_reinitialize_M10()
1779 OUTPLL(pllCLK_PWRMGT_CNTL, tmp); in radeon_reinitialize_M10()
1806 tmp = rinfo->save_regs[2] & 0xff000000; in radeon_reinitialize_M10()
1807 tmp |= MCLK_CNTL__FORCE_MCLKA | in radeon_reinitialize_M10()
1812 OUTPLL(pllMCLK_CNTL, tmp); in radeon_reinitialize_M10()
1815 tmp = INPLL(pllSCLK_CNTL); in radeon_reinitialize_M10()
1816 tmp |= SCLK_CNTL__FORCE_DISP2| in radeon_reinitialize_M10()
1832 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | in radeon_reinitialize_M10()
1844 OUTPLL(pllSCLK_CNTL, tmp); in radeon_reinitialize_M10()
1882 tmp = INPLL(pllSCLK_CNTL2); /* What for ? */ in radeon_reinitialize_M10()
1883 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_reinitialize_M10()
1885 tmp = INPLL(pllSCLK_MORE_CNTL); in radeon_reinitialize_M10()
1886 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */ in radeon_reinitialize_M10()
1889 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_reinitialize_M10()
1979 u32 tmp, i; in radeon_reinitialize_M9P() local
2013 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; in radeon_reinitialize_M9P()
2014 tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT; in radeon_reinitialize_M9P()
2015 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M9P()
2017 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; in radeon_reinitialize_M9P()
2018 tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT; in radeon_reinitialize_M9P()
2019 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M9P()
2031 tmp = rinfo->save_regs[1] in radeon_reinitialize_M9P()
2034 OUTPLL(pllCLK_PWRMGT_CNTL, tmp); in radeon_reinitialize_M9P()
2046 tmp = rinfo->save_regs[2] & 0xff000000; in radeon_reinitialize_M9P()
2047 tmp |= MCLK_CNTL__FORCE_MCLKA | in radeon_reinitialize_M9P()
2053 OUTPLL(pllMCLK_CNTL, tmp); in radeon_reinitialize_M9P()
2056 tmp = 0 | in radeon_reinitialize_M9P()
2071 OUTPLL(pllSCLK_CNTL, tmp); in radeon_reinitialize_M9P()
2104 tmp = rinfo->save_regs[0]; in radeon_reinitialize_M9P()
2105 tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK; in radeon_reinitialize_M9P()
2106 tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK; in radeon_reinitialize_M9P()
2107 OUTPLL(PLL_PWRMGT_CNTL, tmp); in radeon_reinitialize_M9P()
2157 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; in radeon_reinitialize_M9P()
2158 tmp |= rinfo->save_regs[34] & 0xffff0000; in radeon_reinitialize_M9P()
2159 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS; in radeon_reinitialize_M9P()
2160 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_reinitialize_M9P()
2162 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; in radeon_reinitialize_M9P()
2163 tmp |= rinfo->save_regs[34] & 0xffff0000; in radeon_reinitialize_M9P()
2164 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS; in radeon_reinitialize_M9P()
2165 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_reinitialize_M9P()
2180 tmp = INPLL(pllSSPLL_CNTL); in radeon_reinitialize_M9P()
2181 tmp &= ~2; in radeon_reinitialize_M9P()
2182 OUTPLL(pllSSPLL_CNTL, tmp); in radeon_reinitialize_M9P()
2184 tmp &= ~1; in radeon_reinitialize_M9P()
2185 OUTPLL(pllSSPLL_CNTL, tmp); in radeon_reinitialize_M9P()
2187 tmp |= 3; in radeon_reinitialize_M9P()
2188 OUTPLL(pllSSPLL_CNTL, tmp); in radeon_reinitialize_M9P()
2217 u32 tmp, tmp2;
2254 tmp = INPLL(pllVCLK_ECP_CNTL);
2255 OUTPLL(pllVCLK_ECP_CNTL, tmp);
2256 tmp = INPLL(pllPIXCLKS_CNTL);
2257 OUTPLL(pllPIXCLKS_CNTL, tmp);
2271 tmp = INPLL(M_SPLL_REF_FB_DIV);
2272 OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2273 tmp = INPLL(M_SPLL_REF_FB_DIV);
2274 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2277 tmp = INPLL(MPLL_CNTL);
2280 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2283 tmp = INPLL(M_SPLL_REF_FB_DIV);
2284 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2286 tmp = INPLL(MPLL_CNTL);
2287 OUTPLL(MPLL_CNTL, tmp & ~0x2);
2289 tmp = INPLL(MPLL_CNTL);
2290 OUTPLL(MPLL_CNTL, tmp & ~0x1);
2300 tmp = INPLL(SPLL_CNTL);
2303 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2306 tmp = INPLL(M_SPLL_REF_FB_DIV);
2307 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2309 tmp = INPLL(SPLL_CNTL);
2310 OUTPLL(SPLL_CNTL, tmp & ~0x1);
2312 tmp = INPLL(SPLL_CNTL);
2313 OUTPLL(SPLL_CNTL, tmp & ~0x2);
2316 tmp = INPLL(SCLK_CNTL);
2317 OUTPLL(SCLK_CNTL, tmp | 2);
2379 tmp = INREG(FP_GEN_CNTL);
2380 tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2381 OUTREG(FP_GEN_CNTL, tmp);
2383 tmp = INREG(DISP_OUTPUT_CNTL);
2384 tmp &= ~0x400;
2385 OUTREG(DISP_OUTPUT_CNTL, tmp);
2391 tmp = INPLL(MCLK_MISC);
2392 tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2393 OUTPLL(MCLK_MISC, tmp);
2395 tmp = INPLL(SCLK_CNTL);
2396 OUTPLL(SCLK_CNTL, tmp);
2403 tmp = INPLL(VCLK_ECP_CNTL);
2404 OUTPLL(VCLK_ECP_CNTL, tmp);
2406 tmp = INPLL(PPLL_CNTL);
2407 OUTPLL(PPLL_CNTL, tmp);
2411 tmp = INREG(FP_GEN_CNTL);
2413 tmp |= 2;
2414 OUTREG(FP_GEN_CNTL, tmp);
2416 OUTREG(FP_GEN_CNTL, tmp);
2422 tmp = INREG(CRTC_MORE_CNTL);
2423 OUTREG(CRTC_MORE_CNTL, tmp);
2450 tmp = INPLL(PPLL_REF_DIV);
2451 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2452 OUTPLL(PPLL_REF_DIV, tmp);
2460 tmp = INREG(CLOCK_CNTL_INDEX);
2462 OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2468 tmp = INPLL(PPLL_CNTL);
2469 OUTPLL(PPLL_CNTL, tmp & ~0x2);
2471 tmp = INPLL(PPLL_CNTL);
2472 OUTPLL(PPLL_CNTL, tmp & ~0x1);
2475 tmp = INPLL(VCLK_ECP_CNTL);
2476 OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2479 tmp = INPLL(VCLK_ECP_CNTL);
2480 OUTPLL(VCLK_ECP_CNTL, tmp);
2495 tmp = INREG(TMDS_TRANSMITTER_CNTL);
2497 tmp |= TMDS_PLL_EN;
2498 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2500 tmp &= ~TMDS_PLLRST;
2501 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2540 u32 tmp; in radeon_set_suspend() local
2580 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET in radeon_set_suspend()
2582 OUTPLL( pllMDLL_CKO, tmp ); in radeon_set_suspend()