Lines Matching refs:dwidth
808 u32 cycle, u32 dwidth) in tsi148_master_set() argument
948 switch (dwidth) { in tsi148_master_set()
1049 u32 *cycle, u32 *dwidth) in __tsi148_master_get() argument
1090 *dwidth = 0; in __tsi148_master_get()
1149 *dwidth = VME_D16; in __tsi148_master_get()
1151 *dwidth = VME_D32; in __tsi148_master_get()
1159 u32 *cycle, u32 *dwidth) in tsi148_master_get() argument
1166 cycle, dwidth); in tsi148_master_get()
1178 u32 aspace, cycle, dwidth; in tsi148_master_read() local
1191 &cycle, &dwidth); in tsi148_master_read()
1264 u32 aspace, cycle, dwidth; in tsi148_master_write() local
1281 &cycle, &dwidth); in tsi148_master_write()
1418 u32 aspace, u32 cycle, u32 dwidth) in tsi148_dma_set_vme_src_attributes() argument
1460 switch (dwidth) { in tsi148_dma_set_vme_src_attributes()
1517 u32 aspace, u32 cycle, u32 dwidth) in tsi148_dma_set_vme_dest_attributes() argument
1559 switch (dwidth) { in tsi148_dma_set_vme_dest_attributes()
1692 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()
1728 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()