Lines Matching refs:V4L2_HEVC_DPB_ENTRIES_NUM_MAX
134 #define V4L2_HEVC_DPB_ENTRIES_NUM_MAX 16 macro
145 __s8 delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
146 __s8 luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
147 __s8 delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
148 __s8 chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
150 __s8 delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
151 __s8 luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
152 __s8 delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
153 __s8 chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
202 __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
203 __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
220 struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
224 __u8 poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
225 __u8 poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
226 __u8 poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];