Lines Matching refs:cdev
29 struct dma_chan *catpt_dma_request_config_chan(struct catpt_dev *cdev) in catpt_dma_request_config_chan() argument
39 chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev); in catpt_dma_request_config_chan()
41 dev_err(cdev->dev, "request channel failed\n"); in catpt_dma_request_config_chan()
54 dev_err(cdev->dev, "slave config failed: %d\n", ret); in catpt_dma_request_config_chan()
62 static int catpt_dma_memcpy(struct catpt_dev *cdev, struct dma_chan *chan, in catpt_dma_memcpy() argument
72 dev_err(cdev->dev, "prep dma memcpy failed\n"); in catpt_dma_memcpy()
77 catpt_updatel_shim(cdev, HMDC, in catpt_dma_memcpy()
83 catpt_updatel_shim(cdev, HMDC, in catpt_dma_memcpy()
89 int catpt_dma_memcpy_todsp(struct catpt_dev *cdev, struct dma_chan *chan, in catpt_dma_memcpy_todsp() argument
93 return catpt_dma_memcpy(cdev, chan, dst_addr | CATPT_DMA_DSP_ADDR_MASK, in catpt_dma_memcpy_todsp()
97 int catpt_dma_memcpy_fromdsp(struct catpt_dev *cdev, struct dma_chan *chan, in catpt_dma_memcpy_fromdsp() argument
101 return catpt_dma_memcpy(cdev, chan, dst_addr, in catpt_dma_memcpy_fromdsp()
105 int catpt_dmac_probe(struct catpt_dev *cdev) in catpt_dmac_probe() argument
110 dmac = devm_kzalloc(cdev->dev, sizeof(*dmac), GFP_KERNEL); in catpt_dmac_probe()
114 dmac->regs = cdev->lpe_ba + cdev->spec->host_dma_offset[CATPT_DMA_DEVID]; in catpt_dmac_probe()
115 dmac->dev = cdev->dev; in catpt_dmac_probe()
116 dmac->irq = cdev->irq; in catpt_dmac_probe()
118 ret = dma_coerce_mask_and_coherent(cdev->dev, DMA_BIT_MASK(31)); in catpt_dmac_probe()
129 cdev->dmac = dmac; in catpt_dmac_probe()
133 void catpt_dmac_remove(struct catpt_dev *cdev) in catpt_dmac_remove() argument
141 dw_dma_remove(cdev->dmac); in catpt_dmac_remove()
144 static void catpt_dsp_set_srampge(struct catpt_dev *cdev, struct resource *sram, in catpt_dsp_set_srampge() argument
151 old = catpt_readl_pci(cdev, VDRTCTL0) & mask; in catpt_dsp_set_srampge()
152 dev_dbg(cdev->dev, "SRAMPGE [0x%08lx] 0x%08lx -> 0x%08lx", in catpt_dsp_set_srampge()
158 catpt_updatel_pci(cdev, VDRTCTL0, mask, new); in catpt_dsp_set_srampge()
171 dev_dbg(cdev->dev, "sanitize block %ld: off 0x%08x\n", in catpt_dsp_set_srampge()
173 memcpy_fromio(buf, cdev->lpe_ba + off, sizeof(buf)); in catpt_dsp_set_srampge()
179 void catpt_dsp_update_srampge(struct catpt_dev *cdev, struct resource *sram, in catpt_dsp_update_srampge() argument
198 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); in catpt_dsp_update_srampge()
200 catpt_dsp_set_srampge(cdev, sram, mask, new); in catpt_dsp_update_srampge()
203 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, in catpt_dsp_update_srampge()
207 int catpt_dsp_stall(struct catpt_dev *cdev, bool stall) in catpt_dsp_stall() argument
212 catpt_updatel_shim(cdev, CS1, CATPT_CS_STALL, val); in catpt_dsp_stall()
214 return catpt_readl_poll_shim(cdev, CS1, in catpt_dsp_stall()
219 static int catpt_dsp_reset(struct catpt_dev *cdev, bool reset) in catpt_dsp_reset() argument
224 catpt_updatel_shim(cdev, CS1, CATPT_CS_RST, val); in catpt_dsp_reset()
226 return catpt_readl_poll_shim(cdev, CS1, in catpt_dsp_reset()
231 void lpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable) in lpt_dsp_pll_shutdown() argument
236 catpt_updatel_pci(cdev, VDRTCTL0, LPT_VDRTCTL0_APLLSE, val); in lpt_dsp_pll_shutdown()
239 void wpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable) in wpt_dsp_pll_shutdown() argument
244 catpt_updatel_pci(cdev, VDRTCTL2, WPT_VDRTCTL2_APLLSE, val); in wpt_dsp_pll_shutdown()
247 static int catpt_dsp_select_lpclock(struct catpt_dev *cdev, bool lp, bool waiti) in catpt_dsp_select_lpclock() argument
252 mutex_lock(&cdev->clk_mutex); in catpt_dsp_select_lpclock()
255 reg = catpt_readl_shim(cdev, CS1) & CATPT_CS_LPCS; in catpt_dsp_select_lpclock()
256 dev_dbg(cdev->dev, "LPCS [0x%08lx] 0x%08x -> 0x%08x", in catpt_dsp_select_lpclock()
260 mutex_unlock(&cdev->clk_mutex); in catpt_dsp_select_lpclock()
266 ret = catpt_readl_poll_shim(cdev, ISD, in catpt_dsp_select_lpclock()
270 dev_warn(cdev->dev, "await WAITI timeout\n"); in catpt_dsp_select_lpclock()
273 mutex_unlock(&cdev->clk_mutex); in catpt_dsp_select_lpclock()
279 ret = catpt_readl_poll_shim(cdev, CLKCTL, in catpt_dsp_select_lpclock()
283 dev_warn(cdev->dev, "clock change still in progress\n"); in catpt_dsp_select_lpclock()
288 catpt_updatel_shim(cdev, CS1, mask, val); in catpt_dsp_select_lpclock()
290 ret = catpt_readl_poll_shim(cdev, CLKCTL, in catpt_dsp_select_lpclock()
294 dev_warn(cdev->dev, "clock change still in progress\n"); in catpt_dsp_select_lpclock()
297 cdev->spec->pll_shutdown(cdev, lp); in catpt_dsp_select_lpclock()
299 mutex_unlock(&cdev->clk_mutex); in catpt_dsp_select_lpclock()
303 int catpt_dsp_update_lpclock(struct catpt_dev *cdev) in catpt_dsp_update_lpclock() argument
307 list_for_each_entry(stream, &cdev->stream_list, node) in catpt_dsp_update_lpclock()
309 return catpt_dsp_select_lpclock(cdev, false, true); in catpt_dsp_update_lpclock()
311 return catpt_dsp_select_lpclock(cdev, true, true); in catpt_dsp_update_lpclock()
315 static void catpt_dsp_set_regs_defaults(struct catpt_dev *cdev) in catpt_dsp_set_regs_defaults() argument
319 catpt_writel_shim(cdev, CS1, CATPT_CS_DEFAULT); in catpt_dsp_set_regs_defaults()
320 catpt_writel_shim(cdev, ISC, CATPT_ISC_DEFAULT); in catpt_dsp_set_regs_defaults()
321 catpt_writel_shim(cdev, ISD, CATPT_ISD_DEFAULT); in catpt_dsp_set_regs_defaults()
322 catpt_writel_shim(cdev, IMC, CATPT_IMC_DEFAULT); in catpt_dsp_set_regs_defaults()
323 catpt_writel_shim(cdev, IMD, CATPT_IMD_DEFAULT); in catpt_dsp_set_regs_defaults()
324 catpt_writel_shim(cdev, IPCC, CATPT_IPCC_DEFAULT); in catpt_dsp_set_regs_defaults()
325 catpt_writel_shim(cdev, IPCD, CATPT_IPCD_DEFAULT); in catpt_dsp_set_regs_defaults()
326 catpt_writel_shim(cdev, CLKCTL, CATPT_CLKCTL_DEFAULT); in catpt_dsp_set_regs_defaults()
327 catpt_writel_shim(cdev, CS2, CATPT_CS2_DEFAULT); in catpt_dsp_set_regs_defaults()
328 catpt_writel_shim(cdev, LTRC, CATPT_LTRC_DEFAULT); in catpt_dsp_set_regs_defaults()
329 catpt_writel_shim(cdev, HMDC, CATPT_HMDC_DEFAULT); in catpt_dsp_set_regs_defaults()
332 catpt_writel_ssp(cdev, i, SSCR0, CATPT_SSC0_DEFAULT); in catpt_dsp_set_regs_defaults()
333 catpt_writel_ssp(cdev, i, SSCR1, CATPT_SSC1_DEFAULT); in catpt_dsp_set_regs_defaults()
334 catpt_writel_ssp(cdev, i, SSSR, CATPT_SSS_DEFAULT); in catpt_dsp_set_regs_defaults()
335 catpt_writel_ssp(cdev, i, SSITR, CATPT_SSIT_DEFAULT); in catpt_dsp_set_regs_defaults()
336 catpt_writel_ssp(cdev, i, SSDR, CATPT_SSD_DEFAULT); in catpt_dsp_set_regs_defaults()
337 catpt_writel_ssp(cdev, i, SSTO, CATPT_SSTO_DEFAULT); in catpt_dsp_set_regs_defaults()
338 catpt_writel_ssp(cdev, i, SSPSP, CATPT_SSPSP_DEFAULT); in catpt_dsp_set_regs_defaults()
339 catpt_writel_ssp(cdev, i, SSTSA, CATPT_SSTSA_DEFAULT); in catpt_dsp_set_regs_defaults()
340 catpt_writel_ssp(cdev, i, SSRSA, CATPT_SSRSA_DEFAULT); in catpt_dsp_set_regs_defaults()
341 catpt_writel_ssp(cdev, i, SSTSS, CATPT_SSTSS_DEFAULT); in catpt_dsp_set_regs_defaults()
342 catpt_writel_ssp(cdev, i, SSCR2, CATPT_SSCR2_DEFAULT); in catpt_dsp_set_regs_defaults()
343 catpt_writel_ssp(cdev, i, SSPSP2, CATPT_SSPSP2_DEFAULT); in catpt_dsp_set_regs_defaults()
347 int catpt_dsp_power_down(struct catpt_dev *cdev) in catpt_dsp_power_down() argument
352 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); in catpt_dsp_power_down()
354 catpt_dsp_reset(cdev, true); in catpt_dsp_power_down()
356 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), in catpt_dsp_power_down()
358 catpt_dsp_select_lpclock(cdev, true, false); in catpt_dsp_power_down()
360 catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, 0); in catpt_dsp_power_down()
362 catpt_dsp_set_regs_defaults(cdev); in catpt_dsp_power_down()
367 catpt_updatel_pci(cdev, VDRTCTL2, mask, val); in catpt_dsp_power_down()
369 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DTCGE, in catpt_dsp_power_down()
373 catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, in catpt_dsp_power_down()
374 cdev->spec->dram_mask); in catpt_dsp_power_down()
375 catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, in catpt_dsp_power_down()
376 cdev->spec->iram_mask); in catpt_dsp_power_down()
377 mask = cdev->spec->d3srampgd_bit | cdev->spec->d3pgd_bit; in catpt_dsp_power_down()
378 catpt_updatel_pci(cdev, VDRTCTL0, mask, cdev->spec->d3pgd_bit); in catpt_dsp_power_down()
380 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot); in catpt_dsp_power_down()
385 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, in catpt_dsp_power_down()
392 int catpt_dsp_power_up(struct catpt_dev *cdev) in catpt_dsp_power_up() argument
397 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); in catpt_dsp_power_up()
402 catpt_updatel_pci(cdev, VDRTCTL2, mask, val); in catpt_dsp_power_up()
404 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0); in catpt_dsp_power_up()
407 mask = cdev->spec->d3srampgd_bit | cdev->spec->d3pgd_bit; in catpt_dsp_power_up()
408 catpt_updatel_pci(cdev, VDRTCTL0, mask, mask); in catpt_dsp_power_up()
409 catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 0); in catpt_dsp_power_up()
410 catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 0); in catpt_dsp_power_up()
412 catpt_dsp_set_regs_defaults(cdev); in catpt_dsp_power_up()
415 catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, CATPT_CLKCTL_SMOS); in catpt_dsp_power_up()
416 catpt_dsp_select_lpclock(cdev, false, false); in catpt_dsp_power_up()
418 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), in catpt_dsp_power_up()
420 catpt_dsp_reset(cdev, false); in catpt_dsp_power_up()
423 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, in catpt_dsp_power_up()
427 catpt_updatel_shim(cdev, IMC, CATPT_IMC_IPCDB | CATPT_IMC_IPCCD, 0); in catpt_dsp_power_up()
446 int catpt_coredump(struct catpt_dev *cdev) in catpt_coredump() argument
458 dump_size = resource_size(&cdev->dram); in catpt_coredump()
459 dump_size += resource_size(&cdev->iram); in catpt_coredump()
472 hdr->core_id = cdev->spec->core_id; in catpt_coredump()
477 info = cdev->ipc.config.fw_info; in catpt_coredump()
493 hdr->core_id = cdev->spec->core_id; in catpt_coredump()
495 hdr->size = resource_size(&cdev->iram); in catpt_coredump()
498 memcpy_fromio(pos, cdev->lpe_ba + cdev->iram.start, hdr->size); in catpt_coredump()
503 hdr->core_id = cdev->spec->core_id; in catpt_coredump()
505 hdr->size = resource_size(&cdev->dram); in catpt_coredump()
508 memcpy_fromio(pos, cdev->lpe_ba + cdev->dram.start, hdr->size); in catpt_coredump()
513 hdr->core_id = cdev->spec->core_id; in catpt_coredump()
518 memcpy_fromio(pos, catpt_shim_addr(cdev), CATPT_SHIM_REGS_SIZE); in catpt_coredump()
522 memcpy_fromio(pos, catpt_ssp_addr(cdev, i), in catpt_coredump()
527 memcpy_fromio(pos, catpt_dma_addr(cdev, i), in catpt_coredump()
532 dev_coredumpv(cdev->dev, dump, dump_size, GFP_KERNEL); in catpt_coredump()