1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
3
4 #define _RTL8188E_PHYCFG_C_
5
6 #include "../include/osdep_service.h"
7 #include "../include/drv_types.h"
8 #include "../include/rtw_iol.h"
9 #include "../include/rtl8188e_hal.h"
10
11 /*---------------------------Define Local Constant---------------------------*/
12 /* Channel switch:The size of command tables for switch channel*/
13 #define MAX_PRECMD_CNT 16
14 #define MAX_RFDEPENDCMD_CNT 16
15 #define MAX_POSTCMD_CNT 16
16
17 #define MAX_DOZE_WAITING_TIMES_9x 64
18
19 /*---------------------------Define Local Constant---------------------------*/
20
21 /*------------------------Define global variable-----------------------------*/
22
23 /*------------------------Define local variable------------------------------*/
24
25 /*--------------------Define export function prototype-----------------------*/
26 /* Please refer to header file */
27 /*--------------------Define export function prototype-----------------------*/
28
29 /*----------------------------Function Body----------------------------------*/
30 /* */
31 /* 1. BB register R/W API */
32 /* */
33
34 /**
35 * Function: phy_CalculateBitShift
36 *
37 * OverView: Get shifted position of the BitMask
38 *
39 * Input:
40 * u32 BitMask,
41 *
42 * Output: none
43 * Return: u32 Return the shift bit bit position of the mask
44 */
phy_CalculateBitShift(u32 BitMask)45 static u32 phy_CalculateBitShift(u32 BitMask)
46 {
47 u32 i;
48
49 for (i = 0; i <= 31; i++) {
50 if (((BitMask >> i) & 0x1) == 1)
51 break;
52 }
53 return i;
54 }
55
56 /**
57 * Function: PHY_QueryBBReg
58 *
59 * OverView: Read "sepcific bits" from BB register
60 *
61 * Input:
62 * struct adapter *Adapter,
63 * u32 RegAddr, The target address to be readback
64 * u32 BitMask The target bit position in the target address
65 * to be readback
66 * Output: None
67 * Return: u32 Data The readback register value
68 * Note: This function is equal to "GetRegSetting" in PHY programming guide
69 */
70 u32
rtl8188e_PHY_QueryBBReg(struct adapter * Adapter,u32 RegAddr,u32 BitMask)71 rtl8188e_PHY_QueryBBReg(
72 struct adapter *Adapter,
73 u32 RegAddr,
74 u32 BitMask
75 )
76 {
77 u32 ReturnValue = 0, OriginalValue, BitShift;
78
79 OriginalValue = rtw_read32(Adapter, RegAddr);
80 BitShift = phy_CalculateBitShift(BitMask);
81 ReturnValue = (OriginalValue & BitMask) >> BitShift;
82 return ReturnValue;
83 }
84
85 /**
86 * Function: PHY_SetBBReg
87 *
88 * OverView: Write "Specific bits" to BB register (page 8~)
89 *
90 * Input:
91 * struct adapter *Adapter,
92 * u32 RegAddr, The target address to be modified
93 * u32 BitMask The target bit position in the target address
94 * to be modified
95 * u32 Data The new register value in the target bit position
96 * of the target address
97 *
98 * Output: None
99 * Return: None
100 * Note: This function is equal to "PutRegSetting" in PHY programming guide
101 */
102
rtl8188e_PHY_SetBBReg(struct adapter * Adapter,u32 RegAddr,u32 BitMask,u32 Data)103 void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
104 {
105 u32 OriginalValue, BitShift;
106
107 if (BitMask != bMaskDWord) { /* if not "double word" write */
108 OriginalValue = rtw_read32(Adapter, RegAddr);
109 BitShift = phy_CalculateBitShift(BitMask);
110 Data = ((OriginalValue & (~BitMask)) | (Data << BitShift));
111 }
112
113 rtw_write32(Adapter, RegAddr, Data);
114 }
115
116 /* */
117 /* 2. RF register R/W API */
118 /* */
119 /**
120 * Function: phy_RFSerialRead
121 *
122 * OverView: Read regster from RF chips
123 *
124 * Input:
125 * struct adapter *Adapter,
126 * enum rf_radio_path eRFPath, Radio path of A/B/C/D
127 * u32 Offset, The target address to be read
128 *
129 * Output: None
130 * Return: u32 reback value
131 * Note: Threre are three types of serial operations:
132 * 1. Software serial write
133 * 2. Hardware LSSI-Low Speed Serial Interface
134 * 3. Hardware HSSI-High speed
135 * serial write. Driver need to implement (1) and (2).
136 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
137 */
138 static u32
phy_RFSerialRead(struct adapter * Adapter,enum rf_radio_path eRFPath,u32 Offset)139 phy_RFSerialRead(
140 struct adapter *Adapter,
141 enum rf_radio_path eRFPath,
142 u32 Offset
143 )
144 {
145 u32 retValue = 0;
146 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
147 struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
148 u32 NewOffset;
149 u32 tmplong, tmplong2;
150 u8 RfPiEnable = 0;
151 /* */
152 /* Make sure RF register offset is correct */
153 /* */
154 Offset &= 0xff;
155
156 /* */
157 /* Switch page for 8256 RF IC */
158 /* */
159 NewOffset = Offset;
160
161 /* For 92S LSSI Read RFLSSIRead */
162 /* For RF A/B write 0x824/82c(does not work in the future) */
163 /* We must use 0x824 for RF A and B to execute read trigger */
164 tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
165 if (eRFPath == RF_PATH_A)
166 tmplong2 = tmplong;
167 else
168 tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);
169
170 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */
171
172 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong & (~bLSSIReadEdge));
173 udelay(10);/* PlatformStallExecution(10); */
174
175 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
176 udelay(100);/* PlatformStallExecution(100); */
177
178 udelay(10);/* PlatformStallExecution(10); */
179
180 if (eRFPath == RF_PATH_A)
181 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT(8));
182 else if (eRFPath == RF_PATH_B)
183 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT(8));
184
185 if (RfPiEnable) { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
186 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
187 } else { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
188 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
189 }
190 return retValue;
191 }
192
193 /**
194 * Function: phy_RFSerialWrite
195 *
196 * OverView: Write data to RF register (page 8~)
197 *
198 * Input:
199 * struct adapter *Adapter,
200 * enum rf_radio_path eRFPath, Radio path of A/B/C/D
201 * u32 Offset, The target address to be read
202 * u32 Data The new register Data in the target bit position
203 * of the target to be read
204 *
205 * Output: None
206 * Return: None
207 * Note: Threre are three types of serial operations:
208 * 1. Software serial write
209 * 2. Hardware LSSI-Low Speed Serial Interface
210 * 3. Hardware HSSI-High speed
211 * serial write. Driver need to implement (1) and (2).
212 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
213 *
214 * Note: For RF8256 only
215 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
216 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
217 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
218 * programming guide" for more details.
219 * Thus, we define a sub-finction for RTL8526 register address conversion
220 * ===========================================================
221 * Register Mode RegCTL[1] RegCTL[0] Note
222 * (Reg00[12]) (Reg00[10])
223 * ===========================================================
224 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
225 * ------------------------------------------------------------------
226 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
227 * ------------------------------------------------------------------
228 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
229 * ------------------------------------------------------------------
230 *
231 * 2008/09/02 MH Add 92S RF definition
232 *
233 *
234 *
235 */
236 static void
phy_RFSerialWrite(struct adapter * Adapter,enum rf_radio_path eRFPath,u32 Offset,u32 Data)237 phy_RFSerialWrite(
238 struct adapter *Adapter,
239 enum rf_radio_path eRFPath,
240 u32 Offset,
241 u32 Data
242 )
243 {
244 u32 DataAndAddr = 0;
245 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
246 struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
247 u32 NewOffset;
248
249 /* 2009/06/17 MH We can not execute IO for power save or other accident mode. */
250
251 Offset &= 0xff;
252
253 /* */
254 /* Switch page for 8256 RF IC */
255 /* */
256 NewOffset = Offset;
257
258 /* */
259 /* Put write addr in [5:0] and write data in [31:16] */
260 /* */
261 DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */
262
263 /* */
264 /* Write Operation */
265 /* */
266 PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
267 }
268
269 /**
270 * Function: PHY_QueryRFReg
271 *
272 * OverView: Query "Specific bits" to RF register (page 8~)
273 *
274 * Input:
275 * struct adapter *Adapter,
276 * enum rf_radio_path eRFPath, Radio path of A/B/C/D
277 * u32 RegAddr, The target address to be read
278 * u32 BitMask The target bit position in the target address
279 * to be read
280 *
281 * Output: None
282 * Return: u32 Readback value
283 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
284 */
rtl8188e_PHY_QueryRFReg(struct adapter * Adapter,enum rf_radio_path eRFPath,u32 RegAddr,u32 BitMask)285 u32 rtl8188e_PHY_QueryRFReg(struct adapter *Adapter, enum rf_radio_path eRFPath,
286 u32 RegAddr, u32 BitMask)
287 {
288 u32 Original_Value, Readback_Value, BitShift;
289
290 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
291
292 BitShift = phy_CalculateBitShift(BitMask);
293 Readback_Value = (Original_Value & BitMask) >> BitShift;
294 return Readback_Value;
295 }
296
297 /**
298 * Function: PHY_SetRFReg
299 *
300 * OverView: Write "Specific bits" to RF register (page 8~)
301 *
302 * Input:
303 * struct adapter *Adapter,
304 * enum rf_radio_path eRFPath, Radio path of A/B/C/D
305 * u32 RegAddr, The target address to be modified
306 * u32 BitMask The target bit position in the target address
307 * to be modified
308 * u32 Data The new register Data in the target bit position
309 * of the target address
310 *
311 * Output: None
312 * Return: None
313 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
314 */
315 void
rtl8188e_PHY_SetRFReg(struct adapter * Adapter,enum rf_radio_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)316 rtl8188e_PHY_SetRFReg(
317 struct adapter *Adapter,
318 enum rf_radio_path eRFPath,
319 u32 RegAddr,
320 u32 BitMask,
321 u32 Data
322 )
323 {
324 u32 Original_Value, BitShift;
325
326 /* RF data is 12 bits only */
327 if (BitMask != bRFRegOffsetMask) {
328 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
329 BitShift = phy_CalculateBitShift(BitMask);
330 Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
331 }
332
333 phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
334 }
335
336 /* */
337 /* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
338 /* */
339
340 /*-----------------------------------------------------------------------------
341 * Function: PHY_MACConfig8192C
342 *
343 * Overview: Condig MAC by header file or parameter file.
344 *
345 * Input: NONE
346 *
347 * Output: NONE
348 *
349 * Return: NONE
350 *
351 * Revised History:
352 * When Who Remark
353 * 08/12/2008 MHC Create Version 0.
354 *
355 *---------------------------------------------------------------------------*/
PHY_MACConfig8188E(struct adapter * Adapter)356 s32 PHY_MACConfig8188E(struct adapter *Adapter)
357 {
358 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
359 int rtStatus = _SUCCESS;
360
361 /* */
362 /* Config MAC */
363 /* */
364 if (HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv))
365 rtStatus = _FAIL;
366
367 /* 2010.07.13 AMPDU aggregation number B */
368 rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM);
369
370 return rtStatus;
371 }
372
373 /**
374 * Function: phy_InitBBRFRegisterDefinition
375 *
376 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
377 *
378 * Input:
379 * struct adapter *Adapter,
380 *
381 * Output: None
382 * Return: None
383 * Note: The initialization value is constant and it should never be changes
384 */
385 static void
phy_InitBBRFRegisterDefinition(struct adapter * Adapter)386 phy_InitBBRFRegisterDefinition(
387 struct adapter *Adapter
388 )
389 {
390 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
391
392 /* RF Interface Sowrtware Control */
393 pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
394 pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
395 pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 LSBs if read 32-bit from 0x874 */
396 pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
397
398 /* RF Interface Readback Value */
399 pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; /* 16 LSBs if read 32-bit from 0x8E0 */
400 pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;/* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
401 pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;/* 16 LSBs if read 32-bit from 0x8E4 */
402 pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;/* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
403
404 /* RF Interface Output (and Enable) */
405 pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
406 pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
407
408 /* RF Interface (Output and) Enable */
409 pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
410 pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
411
412 /* Addr of LSSI. Wirte RF register by driver */
413 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
414 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
415
416 /* RF parameter */
417 pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; /* BB Band Select */
418 pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
419 pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
420 pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
421
422 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
423 pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
424 pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
425 pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
426 pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */
427
428 /* Tranceiver A~D HSSI Parameter-1 */
429 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; /* wire control parameter1 */
430 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; /* wire control parameter1 */
431
432 /* Tranceiver A~D HSSI Parameter-2 */
433 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */
434 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */
435
436 /* RF switch Control */
437 pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; /* TR/Ant switch control */
438 pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
439 pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
440 pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
441
442 /* AGC control 1 */
443 pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
444 pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
445 pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
446 pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
447
448 /* AGC control 2 */
449 pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
450 pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
451 pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
452 pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
453
454 /* RX AFE control 1 */
455 pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
456 pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
457 pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
458 pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
459
460 /* RX AFE control 1 */
461 pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
462 pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
463 pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
464 pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
465
466 /* Tx AFE control 1 */
467 pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
468 pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
469 pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
470 pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
471
472 /* Tx AFE control 2 */
473 pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
474 pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
475 pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
476 pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
477
478 /* Tranceiver LSSI Readback SI mode */
479 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
480 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
481 pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
482 pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
483
484 /* Tranceiver LSSI Readback PI mode */
485 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
486 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
487 }
488
storePwrIndexDiffRateOffset(struct adapter * Adapter,u32 RegAddr,u32 BitMask,u32 Data)489 void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
490 {
491 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
492
493 if (RegAddr == rTxAGC_A_Rate18_06)
494 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;
495 if (RegAddr == rTxAGC_A_Rate54_24)
496 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;
497 if (RegAddr == rTxAGC_A_CCK1_Mcs32)
498 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;
499 if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)
500 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;
501 if (RegAddr == rTxAGC_A_Mcs03_Mcs00)
502 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;
503 if (RegAddr == rTxAGC_A_Mcs07_Mcs04)
504 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;
505 if (RegAddr == rTxAGC_A_Mcs11_Mcs08)
506 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
507 if (RegAddr == rTxAGC_A_Mcs15_Mcs12) {
508 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
509 if (pHalData->rf_type == RF_1T1R)
510 pHalData->pwrGroupCnt++;
511 }
512 if (RegAddr == rTxAGC_B_Rate18_06)
513 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;
514 if (RegAddr == rTxAGC_B_Rate54_24)
515 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;
516 if (RegAddr == rTxAGC_B_CCK1_55_Mcs32)
517 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;
518 if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
519 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;
520 if (RegAddr == rTxAGC_B_Mcs03_Mcs00)
521 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;
522 if (RegAddr == rTxAGC_B_Mcs07_Mcs04)
523 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;
524 if (RegAddr == rTxAGC_B_Mcs11_Mcs08)
525 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;
526 if (RegAddr == rTxAGC_B_Mcs15_Mcs12) {
527 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;
528 if (pHalData->rf_type != RF_1T1R)
529 pHalData->pwrGroupCnt++;
530 }
531 }
532
phy_BB8188E_Config_ParaFile(struct adapter * Adapter)533 static int phy_BB8188E_Config_ParaFile(struct adapter *Adapter)
534 {
535 struct eeprom_priv *pEEPROM = &Adapter->eeprompriv;
536 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
537 int rtStatus = _SUCCESS;
538
539 /* */
540 /* 1. Read PHY_REG.TXT BB INIT!! */
541 /* We will separate as 88C / 92C according to chip version */
542 /* */
543 if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
544 rtStatus = _FAIL;
545 if (rtStatus != _SUCCESS)
546 goto phy_BB8190_Config_ParaFile_Fail;
547
548 /* 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
549 if (!pEEPROM->bautoload_fail_flag) {
550 pHalData->pwrGroupCnt = 0;
551
552 if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
553 rtStatus = _FAIL;
554 }
555
556 if (rtStatus != _SUCCESS)
557 goto phy_BB8190_Config_ParaFile_Fail;
558
559 /* 3. BB AGC table Initialization */
560 if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
561 rtStatus = _FAIL;
562
563 if (rtStatus != _SUCCESS)
564 goto phy_BB8190_Config_ParaFile_Fail;
565
566 phy_BB8190_Config_ParaFile_Fail:
567
568 return rtStatus;
569 }
570
571 int
PHY_BBConfig8188E(struct adapter * Adapter)572 PHY_BBConfig8188E(
573 struct adapter *Adapter
574 )
575 {
576 int rtStatus = _SUCCESS;
577 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
578 u32 RegVal;
579 u8 CrystalCap;
580
581 phy_InitBBRFRegisterDefinition(Adapter);
582
583 /* Enable BB and RF */
584 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
585 rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT(13) | BIT(0) | BIT(1)));
586
587 /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */
588
589 rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
590
591 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
592
593 /* Config BB and AGC */
594 rtStatus = phy_BB8188E_Config_ParaFile(Adapter);
595
596 /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */
597 CrystalCap = pHalData->CrystalCap & 0x3F;
598 PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));
599
600 return rtStatus;
601 }
602
PHY_RFConfig8188E(struct adapter * Adapter)603 int PHY_RFConfig8188E(struct adapter *Adapter)
604 {
605 int rtStatus = _SUCCESS;
606
607 /* RF config */
608 rtStatus = PHY_RF6052_Config8188E(Adapter);
609 return rtStatus;
610 }
611
getTxPowerIndex88E(struct adapter * Adapter,u8 channel,u8 * cckPowerLevel,u8 * ofdmPowerLevel,u8 * BW20PowerLevel,u8 * BW40PowerLevel)612 static void getTxPowerIndex88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel,
613 u8 *ofdmPowerLevel, u8 *BW20PowerLevel,
614 u8 *BW40PowerLevel)
615 {
616 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
617 u8 index = (channel - 1);
618 u8 TxCount = 0, path_nums;
619
620 if ((RF_1T2R == pHalData->rf_type) || (RF_1T1R == pHalData->rf_type))
621 path_nums = 1;
622 else
623 path_nums = 2;
624
625 for (TxCount = 0; TxCount < path_nums; TxCount++) {
626 if (TxCount == RF_PATH_A) {
627 /* 1. CCK */
628 cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
629 /* 2. OFDM */
630 ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] +
631 pHalData->OFDM_24G_Diff[TxCount][RF_PATH_A];
632 /* 1. BW20 */
633 BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] +
634 pHalData->BW20_24G_Diff[TxCount][RF_PATH_A];
635 /* 2. BW40 */
636 BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
637 } else if (TxCount == RF_PATH_B) {
638 /* 1. CCK */
639 cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
640 /* 2. OFDM */
641 ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] +
642 pHalData->BW20_24G_Diff[RF_PATH_A][index] +
643 pHalData->BW20_24G_Diff[TxCount][index];
644 /* 1. BW20 */
645 BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] +
646 pHalData->BW20_24G_Diff[TxCount][RF_PATH_A] +
647 pHalData->BW20_24G_Diff[TxCount][index];
648 /* 2. BW40 */
649 BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
650 } else if (TxCount == RF_PATH_C) {
651 /* 1. CCK */
652 cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
653 /* 2. OFDM */
654 ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] +
655 pHalData->BW20_24G_Diff[RF_PATH_A][index] +
656 pHalData->BW20_24G_Diff[RF_PATH_B][index] +
657 pHalData->BW20_24G_Diff[TxCount][index];
658 /* 1. BW20 */
659 BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] +
660 pHalData->BW20_24G_Diff[RF_PATH_A][index] +
661 pHalData->BW20_24G_Diff[RF_PATH_B][index] +
662 pHalData->BW20_24G_Diff[TxCount][index];
663 /* 2. BW40 */
664 BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
665 } else if (TxCount == RF_PATH_D) {
666 /* 1. CCK */
667 cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
668 /* 2. OFDM */
669 ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] +
670 pHalData->BW20_24G_Diff[RF_PATH_A][index] +
671 pHalData->BW20_24G_Diff[RF_PATH_B][index] +
672 pHalData->BW20_24G_Diff[RF_PATH_C][index] +
673 pHalData->BW20_24G_Diff[TxCount][index];
674
675 /* 1. BW20 */
676 BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index] +
677 pHalData->BW20_24G_Diff[RF_PATH_A][index] +
678 pHalData->BW20_24G_Diff[RF_PATH_B][index] +
679 pHalData->BW20_24G_Diff[RF_PATH_C][index] +
680 pHalData->BW20_24G_Diff[TxCount][index];
681
682 /* 2. BW40 */
683 BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
684 }
685 }
686 }
687
phy_PowerIndexCheck88E(struct adapter * Adapter,u8 channel,u8 * cckPowerLevel,u8 * ofdmPowerLevel,u8 * BW20PowerLevel,u8 * BW40PowerLevel)688 static void phy_PowerIndexCheck88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel,
689 u8 *ofdmPowerLevel, u8 *BW20PowerLevel, u8 *BW40PowerLevel)
690 {
691 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
692
693 pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
694 pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
695 pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0];
696 pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0];
697 }
698
699 /*-----------------------------------------------------------------------------
700 * Function: SetTxPowerLevel8190()
701 *
702 * Overview: This function is export to "HalCommon" moudule
703 * We must consider RF path later!!!!!!!
704 *
705 * Input: struct adapter *Adapter
706 * u8 channel
707 *
708 * Output: NONE
709 *
710 * Return: NONE
711 * 2008/11/04 MHC We remove EEPROM_93C56.
712 * We need to move CCX relative code to independet file.
713 * 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
714 *
715 *---------------------------------------------------------------------------*/
716 void
PHY_SetTxPowerLevel8188E(struct adapter * Adapter,u8 channel)717 PHY_SetTxPowerLevel8188E(
718 struct adapter *Adapter,
719 u8 channel
720 )
721 {
722 u8 cckPowerLevel[MAX_TX_COUNT] = {0};
723 u8 ofdmPowerLevel[MAX_TX_COUNT] = {0};/* [0]:RF-A, [1]:RF-B */
724 u8 BW20PowerLevel[MAX_TX_COUNT] = {0};
725 u8 BW40PowerLevel[MAX_TX_COUNT] = {0};
726
727 getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]);
728
729 phy_PowerIndexCheck88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]);
730
731 rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
732 rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0], channel);
733 }
734
735 /*-----------------------------------------------------------------------------
736 * Function: PHY_SetBWModeCallback8192C()
737 *
738 * Overview: Timer callback function for SetSetBWMode
739 *
740 * Input: PRT_TIMER pTimer
741 *
742 * Output: NONE
743 *
744 * Return: NONE
745 *
746 * Note: (1) We do not take j mode into consideration now
747 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
748 * concurrently?
749 *---------------------------------------------------------------------------*/
750 static void
_PHY_SetBWMode92C(struct adapter * Adapter)751 _PHY_SetBWMode92C(
752 struct adapter *Adapter
753 )
754 {
755 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
756 u8 regBwOpMode;
757 u8 regRRSR_RSC;
758
759 if (pHalData->rf_chip == RF_PSEUDO_11N)
760 return;
761
762 /* There is no 40MHz mode in RF_8225. */
763 if (pHalData->rf_chip == RF_8225)
764 return;
765
766 if (Adapter->bDriverStopped)
767 return;
768
769 /* 3 */
770 /* 3<1>Set MAC register */
771 /* 3 */
772
773 regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
774 regRRSR_RSC = rtw_read8(Adapter, REG_RRSR + 2);
775
776 switch (pHalData->CurrentChannelBW) {
777 case HT_CHANNEL_WIDTH_20:
778 regBwOpMode |= BW_OPMODE_20MHZ;
779 /* 2007/02/07 Mark by Emily because we have not verify whether this register works */
780 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
781 break;
782 case HT_CHANNEL_WIDTH_40:
783 regBwOpMode &= ~BW_OPMODE_20MHZ;
784 /* 2007/02/07 Mark by Emily because we have not verify whether this register works */
785 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
786 regRRSR_RSC = (regRRSR_RSC & 0x90) | (pHalData->nCur40MhzPrimeSC << 5);
787 rtw_write8(Adapter, REG_RRSR + 2, regRRSR_RSC);
788 break;
789 default:
790 break;
791 }
792
793 /* 3 */
794 /* 3 <2>Set PHY related register */
795 /* 3 */
796 switch (pHalData->CurrentChannelBW) {
797 /* 20 MHz channel*/
798 case HT_CHANNEL_WIDTH_20:
799 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
800 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
801 break;
802 /* 40 MHz channel*/
803 case HT_CHANNEL_WIDTH_40:
804 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
805 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
806 /* Set Control channel to upper or lower. These settings are required only for 40MHz */
807 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
808 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
809 PHY_SetBBReg(Adapter, 0x818, (BIT(26) | BIT(27)),
810 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
811 break;
812 default:
813 break;
814 }
815 /* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */
816
817 /* 3<3>Set RF related register */
818 switch (pHalData->rf_chip) {
819 case RF_8225:
820 break;
821 case RF_8256:
822 /* Please implement this function in Hal8190PciPhy8256.c */
823 break;
824 case RF_PSEUDO_11N:
825 break;
826 case RF_6052:
827 rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);
828 break;
829 default:
830 break;
831 }
832 }
833
834 /*-----------------------------------------------------------------------------
835 * Function: SetBWMode8190Pci()
836 *
837 * Overview: This function is export to "HalCommon" moudule
838 *
839 * Input: struct adapter *Adapter
840 * enum ht_channel_width Bandwidth 20M or 40M
841 *
842 * Output: NONE
843 *
844 * Return: NONE
845 *
846 * Note: We do not take j mode into consideration now
847 *---------------------------------------------------------------------------*/
PHY_SetBWMode8188E(struct adapter * Adapter,enum ht_channel_width Bandwidth,unsigned char Offset)848 void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth, /* 20M or 40M */
849 unsigned char Offset) /* Upper, Lower, or Don't care */
850 {
851 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
852 enum ht_channel_width tmpBW = pHalData->CurrentChannelBW;
853
854 pHalData->CurrentChannelBW = Bandwidth;
855
856 pHalData->nCur40MhzPrimeSC = Offset;
857
858 if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
859 _PHY_SetBWMode92C(Adapter);
860 else
861 pHalData->CurrentChannelBW = tmpBW;
862 }
863
_PHY_SwChnl8192C(struct adapter * Adapter,u8 channel)864 static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel)
865 {
866 u8 eRFPath = 0;
867 u32 param1, param2;
868 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
869
870 if (Adapter->bNotifyChannelChange)
871 DBG_88E("[%s] ch = %d\n", __func__, channel);
872
873 /* s1. pre common command - CmdID_SetTxPowerLevel */
874 PHY_SetTxPowerLevel8188E(Adapter, channel);
875
876 /* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */
877 param1 = RF_CHNLBW;
878 param2 = channel;
879 pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
880 PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
881 }
882
PHY_SwChnl8188E(struct adapter * Adapter,u8 channel)883 void PHY_SwChnl8188E(struct adapter *Adapter, u8 channel)
884 {
885 /* Call after initialization */
886 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
887
888 if (pHalData->rf_chip == RF_PSEUDO_11N)
889 return; /* return immediately if it is peudo-phy */
890
891 if (channel == 0)
892 channel = 1;
893
894 if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
895 pHalData->CurrentChannel = channel;
896 _PHY_SwChnl8192C(Adapter, channel);
897 }
898 }
899