1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/kvm_host.h>
15 #include <linux/mm.h>
16 #include <linux/printk.h>
17 #include <linux/uaccess.h>
18
19 #include <asm/cacheflush.h>
20 #include <asm/cputype.h>
21 #include <asm/debug-monitors.h>
22 #include <asm/esr.h>
23 #include <asm/kvm_arm.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_hyp.h>
26 #include <asm/kvm_mmu.h>
27 #include <asm/perf_event.h>
28 #include <asm/sysreg.h>
29
30 #include <trace/events/kvm.h>
31
32 #include "sys_regs.h"
33
34 #include "trace.h"
35
36 /*
37 * All of this file is extremely similar to the ARM coproc.c, but the
38 * types are different. My gut feeling is that it should be pretty
39 * easy to merge, but that would be an ABI breakage -- again. VFP
40 * would also need to be abstracted.
41 *
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
44 * 64bit interface.
45 */
46
read_from_write_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)47 static bool read_from_write_only(struct kvm_vcpu *vcpu,
48 struct sys_reg_params *params,
49 const struct sys_reg_desc *r)
50 {
51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
52 print_sys_reg_instr(params);
53 kvm_inject_undefined(vcpu);
54 return false;
55 }
56
write_to_read_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)57 static bool write_to_read_only(struct kvm_vcpu *vcpu,
58 struct sys_reg_params *params,
59 const struct sys_reg_desc *r)
60 {
61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
62 print_sys_reg_instr(params);
63 kvm_inject_undefined(vcpu);
64 return false;
65 }
66
vcpu_read_sys_reg(const struct kvm_vcpu * vcpu,int reg)67 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
68 {
69 u64 val = 0x8badf00d8badf00d;
70
71 if (vcpu->arch.sysregs_loaded_on_cpu &&
72 __vcpu_read_sys_reg_from_cpu(reg, &val))
73 return val;
74
75 return __vcpu_sys_reg(vcpu, reg);
76 }
77
vcpu_write_sys_reg(struct kvm_vcpu * vcpu,u64 val,int reg)78 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
79 {
80 if (vcpu->arch.sysregs_loaded_on_cpu &&
81 __vcpu_write_sys_reg_to_cpu(val, reg))
82 return;
83
84 __vcpu_sys_reg(vcpu, reg) = val;
85 }
86
87 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
88 static u32 cache_levels;
89
90 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
91 #define CSSELR_MAX 14
92
93 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(u32 csselr)94 static u32 get_ccsidr(u32 csselr)
95 {
96 u32 ccsidr;
97
98 /* Make sure noone else changes CSSELR during this! */
99 local_irq_disable();
100 write_sysreg(csselr, csselr_el1);
101 isb();
102 ccsidr = read_sysreg(ccsidr_el1);
103 local_irq_enable();
104
105 return ccsidr;
106 }
107
108 /*
109 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
110 */
access_dcsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)111 static bool access_dcsw(struct kvm_vcpu *vcpu,
112 struct sys_reg_params *p,
113 const struct sys_reg_desc *r)
114 {
115 if (!p->is_write)
116 return read_from_write_only(vcpu, p, r);
117
118 /*
119 * Only track S/W ops if we don't have FWB. It still indicates
120 * that the guest is a bit broken (S/W operations should only
121 * be done by firmware, knowing that there is only a single
122 * CPU left in the system, and certainly not from non-secure
123 * software).
124 */
125 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
126 kvm_set_way_flush(vcpu);
127
128 return true;
129 }
130
get_access_mask(const struct sys_reg_desc * r,u64 * mask,u64 * shift)131 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
132 {
133 switch (r->aarch32_map) {
134 case AA32_LO:
135 *mask = GENMASK_ULL(31, 0);
136 *shift = 0;
137 break;
138 case AA32_HI:
139 *mask = GENMASK_ULL(63, 32);
140 *shift = 32;
141 break;
142 default:
143 *mask = GENMASK_ULL(63, 0);
144 *shift = 0;
145 break;
146 }
147 }
148
149 /*
150 * Generic accessor for VM registers. Only called as long as HCR_TVM
151 * is set. If the guest enables the MMU, we stop trapping the VM
152 * sys_regs and leave it in complete control of the caches.
153 */
access_vm_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)154 static bool access_vm_reg(struct kvm_vcpu *vcpu,
155 struct sys_reg_params *p,
156 const struct sys_reg_desc *r)
157 {
158 bool was_enabled = vcpu_has_cache_enabled(vcpu);
159 u64 val, mask, shift;
160
161 BUG_ON(!p->is_write);
162
163 get_access_mask(r, &mask, &shift);
164
165 if (~mask) {
166 val = vcpu_read_sys_reg(vcpu, r->reg);
167 val &= ~mask;
168 } else {
169 val = 0;
170 }
171
172 val |= (p->regval & (mask >> shift)) << shift;
173 vcpu_write_sys_reg(vcpu, val, r->reg);
174
175 kvm_toggle_cache(vcpu, was_enabled);
176 return true;
177 }
178
access_actlr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)179 static bool access_actlr(struct kvm_vcpu *vcpu,
180 struct sys_reg_params *p,
181 const struct sys_reg_desc *r)
182 {
183 u64 mask, shift;
184
185 if (p->is_write)
186 return ignore_write(vcpu, p);
187
188 get_access_mask(r, &mask, &shift);
189 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
190
191 return true;
192 }
193
194 /*
195 * Trap handler for the GICv3 SGI generation system register.
196 * Forward the request to the VGIC emulation.
197 * The cp15_64 code makes sure this automatically works
198 * for both AArch64 and AArch32 accesses.
199 */
access_gic_sgi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)200 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
201 struct sys_reg_params *p,
202 const struct sys_reg_desc *r)
203 {
204 bool g1;
205
206 if (!p->is_write)
207 return read_from_write_only(vcpu, p, r);
208
209 /*
210 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
211 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
212 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
213 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
214 * group.
215 */
216 if (p->Op0 == 0) { /* AArch32 */
217 switch (p->Op1) {
218 default: /* Keep GCC quiet */
219 case 0: /* ICC_SGI1R */
220 g1 = true;
221 break;
222 case 1: /* ICC_ASGI1R */
223 case 2: /* ICC_SGI0R */
224 g1 = false;
225 break;
226 }
227 } else { /* AArch64 */
228 switch (p->Op2) {
229 default: /* Keep GCC quiet */
230 case 5: /* ICC_SGI1R_EL1 */
231 g1 = true;
232 break;
233 case 6: /* ICC_ASGI1R_EL1 */
234 case 7: /* ICC_SGI0R_EL1 */
235 g1 = false;
236 break;
237 }
238 }
239
240 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
241
242 return true;
243 }
244
access_gic_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)245 static bool access_gic_sre(struct kvm_vcpu *vcpu,
246 struct sys_reg_params *p,
247 const struct sys_reg_desc *r)
248 {
249 if (p->is_write)
250 return ignore_write(vcpu, p);
251
252 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
253 return true;
254 }
255
trap_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)256 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
257 struct sys_reg_params *p,
258 const struct sys_reg_desc *r)
259 {
260 if (p->is_write)
261 return ignore_write(vcpu, p);
262 else
263 return read_zero(vcpu, p);
264 }
265
266 /*
267 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
268 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
269 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
270 * treat it separately.
271 */
trap_loregion(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)272 static bool trap_loregion(struct kvm_vcpu *vcpu,
273 struct sys_reg_params *p,
274 const struct sys_reg_desc *r)
275 {
276 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
277 u32 sr = reg_to_encoding(r);
278
279 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
280 kvm_inject_undefined(vcpu);
281 return false;
282 }
283
284 if (p->is_write && sr == SYS_LORID_EL1)
285 return write_to_read_only(vcpu, p, r);
286
287 return trap_raz_wi(vcpu, p, r);
288 }
289
trap_oslsr_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)290 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
291 struct sys_reg_params *p,
292 const struct sys_reg_desc *r)
293 {
294 if (p->is_write) {
295 return ignore_write(vcpu, p);
296 } else {
297 p->regval = (1 << 3);
298 return true;
299 }
300 }
301
trap_dbgauthstatus_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)302 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
303 struct sys_reg_params *p,
304 const struct sys_reg_desc *r)
305 {
306 if (p->is_write) {
307 return ignore_write(vcpu, p);
308 } else {
309 p->regval = read_sysreg(dbgauthstatus_el1);
310 return true;
311 }
312 }
313
314 /*
315 * We want to avoid world-switching all the DBG registers all the
316 * time:
317 *
318 * - If we've touched any debug register, it is likely that we're
319 * going to touch more of them. It then makes sense to disable the
320 * traps and start doing the save/restore dance
321 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
322 * then mandatory to save/restore the registers, as the guest
323 * depends on them.
324 *
325 * For this, we use a DIRTY bit, indicating the guest has modified the
326 * debug registers, used as follow:
327 *
328 * On guest entry:
329 * - If the dirty bit is set (because we're coming back from trapping),
330 * disable the traps, save host registers, restore guest registers.
331 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
332 * set the dirty bit, disable the traps, save host registers,
333 * restore guest registers.
334 * - Otherwise, enable the traps
335 *
336 * On guest exit:
337 * - If the dirty bit is set, save guest registers, restore host
338 * registers and clear the dirty bit. This ensure that the host can
339 * now use the debug registers.
340 */
trap_debug_regs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)341 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
342 struct sys_reg_params *p,
343 const struct sys_reg_desc *r)
344 {
345 if (p->is_write) {
346 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
347 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
348 } else {
349 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
350 }
351
352 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
353
354 return true;
355 }
356
357 /*
358 * reg_to_dbg/dbg_to_reg
359 *
360 * A 32 bit write to a debug register leave top bits alone
361 * A 32 bit read from a debug register only returns the bottom bits
362 *
363 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
364 * hyp.S code switches between host and guest values in future.
365 */
reg_to_dbg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)366 static void reg_to_dbg(struct kvm_vcpu *vcpu,
367 struct sys_reg_params *p,
368 const struct sys_reg_desc *rd,
369 u64 *dbg_reg)
370 {
371 u64 mask, shift, val;
372
373 get_access_mask(rd, &mask, &shift);
374
375 val = *dbg_reg;
376 val &= ~mask;
377 val |= (p->regval & (mask >> shift)) << shift;
378 *dbg_reg = val;
379
380 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
381 }
382
dbg_to_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)383 static void dbg_to_reg(struct kvm_vcpu *vcpu,
384 struct sys_reg_params *p,
385 const struct sys_reg_desc *rd,
386 u64 *dbg_reg)
387 {
388 u64 mask, shift;
389
390 get_access_mask(rd, &mask, &shift);
391 p->regval = (*dbg_reg & mask) >> shift;
392 }
393
trap_bvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)394 static bool trap_bvr(struct kvm_vcpu *vcpu,
395 struct sys_reg_params *p,
396 const struct sys_reg_desc *rd)
397 {
398 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
399
400 if (p->is_write)
401 reg_to_dbg(vcpu, p, rd, dbg_reg);
402 else
403 dbg_to_reg(vcpu, p, rd, dbg_reg);
404
405 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
406
407 return true;
408 }
409
set_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)410 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
411 const struct kvm_one_reg *reg, void __user *uaddr)
412 {
413 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
414
415 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
416 return -EFAULT;
417 return 0;
418 }
419
get_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)420 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
421 const struct kvm_one_reg *reg, void __user *uaddr)
422 {
423 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
424
425 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
426 return -EFAULT;
427 return 0;
428 }
429
reset_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)430 static void reset_bvr(struct kvm_vcpu *vcpu,
431 const struct sys_reg_desc *rd)
432 {
433 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
434 }
435
trap_bcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)436 static bool trap_bcr(struct kvm_vcpu *vcpu,
437 struct sys_reg_params *p,
438 const struct sys_reg_desc *rd)
439 {
440 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
441
442 if (p->is_write)
443 reg_to_dbg(vcpu, p, rd, dbg_reg);
444 else
445 dbg_to_reg(vcpu, p, rd, dbg_reg);
446
447 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
448
449 return true;
450 }
451
set_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)452 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
453 const struct kvm_one_reg *reg, void __user *uaddr)
454 {
455 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
456
457 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
458 return -EFAULT;
459
460 return 0;
461 }
462
get_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)463 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
464 const struct kvm_one_reg *reg, void __user *uaddr)
465 {
466 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
467
468 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
469 return -EFAULT;
470 return 0;
471 }
472
reset_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)473 static void reset_bcr(struct kvm_vcpu *vcpu,
474 const struct sys_reg_desc *rd)
475 {
476 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
477 }
478
trap_wvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)479 static bool trap_wvr(struct kvm_vcpu *vcpu,
480 struct sys_reg_params *p,
481 const struct sys_reg_desc *rd)
482 {
483 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
484
485 if (p->is_write)
486 reg_to_dbg(vcpu, p, rd, dbg_reg);
487 else
488 dbg_to_reg(vcpu, p, rd, dbg_reg);
489
490 trace_trap_reg(__func__, rd->CRm, p->is_write,
491 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
492
493 return true;
494 }
495
set_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)496 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
497 const struct kvm_one_reg *reg, void __user *uaddr)
498 {
499 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
500
501 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
502 return -EFAULT;
503 return 0;
504 }
505
get_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)506 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
507 const struct kvm_one_reg *reg, void __user *uaddr)
508 {
509 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
510
511 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
512 return -EFAULT;
513 return 0;
514 }
515
reset_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)516 static void reset_wvr(struct kvm_vcpu *vcpu,
517 const struct sys_reg_desc *rd)
518 {
519 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
520 }
521
trap_wcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)522 static bool trap_wcr(struct kvm_vcpu *vcpu,
523 struct sys_reg_params *p,
524 const struct sys_reg_desc *rd)
525 {
526 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
527
528 if (p->is_write)
529 reg_to_dbg(vcpu, p, rd, dbg_reg);
530 else
531 dbg_to_reg(vcpu, p, rd, dbg_reg);
532
533 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
534
535 return true;
536 }
537
set_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)538 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
539 const struct kvm_one_reg *reg, void __user *uaddr)
540 {
541 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
542
543 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
544 return -EFAULT;
545 return 0;
546 }
547
get_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)548 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
549 const struct kvm_one_reg *reg, void __user *uaddr)
550 {
551 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
552
553 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
554 return -EFAULT;
555 return 0;
556 }
557
reset_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)558 static void reset_wcr(struct kvm_vcpu *vcpu,
559 const struct sys_reg_desc *rd)
560 {
561 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
562 }
563
reset_amair_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)564 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
565 {
566 u64 amair = read_sysreg(amair_el1);
567 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
568 }
569
reset_actlr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)570 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
571 {
572 u64 actlr = read_sysreg(actlr_el1);
573 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
574 }
575
reset_mpidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)576 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
577 {
578 u64 mpidr;
579
580 /*
581 * Map the vcpu_id into the first three affinity level fields of
582 * the MPIDR. We limit the number of VCPUs in level 0 due to a
583 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
584 * of the GICv3 to be able to address each CPU directly when
585 * sending IPIs.
586 */
587 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
588 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
589 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
590 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
591 }
592
pmu_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)593 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
594 const struct sys_reg_desc *r)
595 {
596 if (kvm_vcpu_has_pmu(vcpu))
597 return 0;
598
599 return REG_HIDDEN;
600 }
601
reset_pmu_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)602 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
603 {
604 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
605
606 /* No PMU available, any PMU reg may UNDEF... */
607 if (!kvm_arm_support_pmu_v3())
608 return;
609
610 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
611 n &= ARMV8_PMU_PMCR_N_MASK;
612 if (n)
613 mask |= GENMASK(n - 1, 0);
614
615 reset_unknown(vcpu, r);
616 __vcpu_sys_reg(vcpu, r->reg) &= mask;
617 }
618
reset_pmevcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)619 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
620 {
621 reset_unknown(vcpu, r);
622 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
623 }
624
reset_pmevtyper(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)625 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
626 {
627 reset_unknown(vcpu, r);
628 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
629 }
630
reset_pmselr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)631 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
632 {
633 reset_unknown(vcpu, r);
634 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
635 }
636
reset_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)637 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
638 {
639 u64 pmcr, val;
640
641 /* No PMU available, PMCR_EL0 may UNDEF... */
642 if (!kvm_arm_support_pmu_v3())
643 return;
644
645 pmcr = read_sysreg(pmcr_el0);
646 /*
647 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
648 * except PMCR.E resetting to zero.
649 */
650 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
651 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
652 if (!system_supports_32bit_el0())
653 val |= ARMV8_PMU_PMCR_LC;
654 __vcpu_sys_reg(vcpu, r->reg) = val;
655 }
656
check_pmu_access_disabled(struct kvm_vcpu * vcpu,u64 flags)657 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
658 {
659 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
660 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
661
662 if (!enabled)
663 kvm_inject_undefined(vcpu);
664
665 return !enabled;
666 }
667
pmu_access_el0_disabled(struct kvm_vcpu * vcpu)668 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
669 {
670 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
671 }
672
pmu_write_swinc_el0_disabled(struct kvm_vcpu * vcpu)673 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
674 {
675 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
676 }
677
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu * vcpu)678 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
679 {
680 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
681 }
682
pmu_access_event_counter_el0_disabled(struct kvm_vcpu * vcpu)683 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
684 {
685 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
686 }
687
access_pmcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)688 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
689 const struct sys_reg_desc *r)
690 {
691 u64 val;
692
693 if (pmu_access_el0_disabled(vcpu))
694 return false;
695
696 if (p->is_write) {
697 /* Only update writeable bits of PMCR */
698 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
699 val &= ~ARMV8_PMU_PMCR_MASK;
700 val |= p->regval & ARMV8_PMU_PMCR_MASK;
701 if (!system_supports_32bit_el0())
702 val |= ARMV8_PMU_PMCR_LC;
703 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
704 kvm_pmu_handle_pmcr(vcpu, val);
705 kvm_vcpu_pmu_restore_guest(vcpu);
706 } else {
707 /* PMCR.P & PMCR.C are RAZ */
708 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
709 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
710 p->regval = val;
711 }
712
713 return true;
714 }
715
access_pmselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)716 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
717 const struct sys_reg_desc *r)
718 {
719 if (pmu_access_event_counter_el0_disabled(vcpu))
720 return false;
721
722 if (p->is_write)
723 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
724 else
725 /* return PMSELR.SEL field */
726 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
727 & ARMV8_PMU_COUNTER_MASK;
728
729 return true;
730 }
731
access_pmceid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)732 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
733 const struct sys_reg_desc *r)
734 {
735 u64 pmceid, mask, shift;
736
737 BUG_ON(p->is_write);
738
739 if (pmu_access_el0_disabled(vcpu))
740 return false;
741
742 get_access_mask(r, &mask, &shift);
743
744 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
745 pmceid &= mask;
746 pmceid >>= shift;
747
748 p->regval = pmceid;
749
750 return true;
751 }
752
pmu_counter_idx_valid(struct kvm_vcpu * vcpu,u64 idx)753 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
754 {
755 u64 pmcr, val;
756
757 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
758 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
759 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
760 kvm_inject_undefined(vcpu);
761 return false;
762 }
763
764 return true;
765 }
766
access_pmu_evcntr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)767 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
768 struct sys_reg_params *p,
769 const struct sys_reg_desc *r)
770 {
771 u64 idx = ~0UL;
772
773 if (r->CRn == 9 && r->CRm == 13) {
774 if (r->Op2 == 2) {
775 /* PMXEVCNTR_EL0 */
776 if (pmu_access_event_counter_el0_disabled(vcpu))
777 return false;
778
779 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
780 & ARMV8_PMU_COUNTER_MASK;
781 } else if (r->Op2 == 0) {
782 /* PMCCNTR_EL0 */
783 if (pmu_access_cycle_counter_el0_disabled(vcpu))
784 return false;
785
786 idx = ARMV8_PMU_CYCLE_IDX;
787 }
788 } else if (r->CRn == 0 && r->CRm == 9) {
789 /* PMCCNTR */
790 if (pmu_access_event_counter_el0_disabled(vcpu))
791 return false;
792
793 idx = ARMV8_PMU_CYCLE_IDX;
794 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
795 /* PMEVCNTRn_EL0 */
796 if (pmu_access_event_counter_el0_disabled(vcpu))
797 return false;
798
799 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
800 }
801
802 /* Catch any decoding mistake */
803 WARN_ON(idx == ~0UL);
804
805 if (!pmu_counter_idx_valid(vcpu, idx))
806 return false;
807
808 if (p->is_write) {
809 if (pmu_access_el0_disabled(vcpu))
810 return false;
811
812 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
813 } else {
814 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
815 }
816
817 return true;
818 }
819
access_pmu_evtyper(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)820 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
821 const struct sys_reg_desc *r)
822 {
823 u64 idx, reg;
824
825 if (pmu_access_el0_disabled(vcpu))
826 return false;
827
828 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
829 /* PMXEVTYPER_EL0 */
830 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
831 reg = PMEVTYPER0_EL0 + idx;
832 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
833 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
834 if (idx == ARMV8_PMU_CYCLE_IDX)
835 reg = PMCCFILTR_EL0;
836 else
837 /* PMEVTYPERn_EL0 */
838 reg = PMEVTYPER0_EL0 + idx;
839 } else {
840 BUG();
841 }
842
843 if (!pmu_counter_idx_valid(vcpu, idx))
844 return false;
845
846 if (p->is_write) {
847 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
848 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
849 kvm_vcpu_pmu_restore_guest(vcpu);
850 } else {
851 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
852 }
853
854 return true;
855 }
856
access_pmcnten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)857 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
858 const struct sys_reg_desc *r)
859 {
860 u64 val, mask;
861
862 if (pmu_access_el0_disabled(vcpu))
863 return false;
864
865 mask = kvm_pmu_valid_counter_mask(vcpu);
866 if (p->is_write) {
867 val = p->regval & mask;
868 if (r->Op2 & 0x1) {
869 /* accessing PMCNTENSET_EL0 */
870 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
871 kvm_pmu_enable_counter_mask(vcpu, val);
872 kvm_vcpu_pmu_restore_guest(vcpu);
873 } else {
874 /* accessing PMCNTENCLR_EL0 */
875 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
876 kvm_pmu_disable_counter_mask(vcpu, val);
877 }
878 } else {
879 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
880 }
881
882 return true;
883 }
884
access_pminten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)885 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
886 const struct sys_reg_desc *r)
887 {
888 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
889
890 if (check_pmu_access_disabled(vcpu, 0))
891 return false;
892
893 if (p->is_write) {
894 u64 val = p->regval & mask;
895
896 if (r->Op2 & 0x1)
897 /* accessing PMINTENSET_EL1 */
898 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
899 else
900 /* accessing PMINTENCLR_EL1 */
901 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
902 } else {
903 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
904 }
905
906 return true;
907 }
908
access_pmovs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)909 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
910 const struct sys_reg_desc *r)
911 {
912 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
913
914 if (pmu_access_el0_disabled(vcpu))
915 return false;
916
917 if (p->is_write) {
918 if (r->CRm & 0x2)
919 /* accessing PMOVSSET_EL0 */
920 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
921 else
922 /* accessing PMOVSCLR_EL0 */
923 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
924 } else {
925 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
926 }
927
928 return true;
929 }
930
access_pmswinc(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)931 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
932 const struct sys_reg_desc *r)
933 {
934 u64 mask;
935
936 if (!p->is_write)
937 return read_from_write_only(vcpu, p, r);
938
939 if (pmu_write_swinc_el0_disabled(vcpu))
940 return false;
941
942 mask = kvm_pmu_valid_counter_mask(vcpu);
943 kvm_pmu_software_increment(vcpu, p->regval & mask);
944 return true;
945 }
946
access_pmuserenr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)947 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
948 const struct sys_reg_desc *r)
949 {
950 if (p->is_write) {
951 if (!vcpu_mode_priv(vcpu)) {
952 kvm_inject_undefined(vcpu);
953 return false;
954 }
955
956 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
957 p->regval & ARMV8_PMU_USERENR_MASK;
958 } else {
959 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
960 & ARMV8_PMU_USERENR_MASK;
961 }
962
963 return true;
964 }
965
966 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
967 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
968 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
969 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
970 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
971 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
972 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
973 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
974 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
975 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
976
977 #define PMU_SYS_REG(r) \
978 SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility
979
980 /* Macro to expand the PMEVCNTRn_EL0 register */
981 #define PMU_PMEVCNTR_EL0(n) \
982 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \
983 .reset = reset_pmevcntr, \
984 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
985
986 /* Macro to expand the PMEVTYPERn_EL0 register */
987 #define PMU_PMEVTYPER_EL0(n) \
988 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \
989 .reset = reset_pmevtyper, \
990 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
991
undef_access(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)992 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
993 const struct sys_reg_desc *r)
994 {
995 kvm_inject_undefined(vcpu);
996
997 return false;
998 }
999
1000 /* Macro to expand the AMU counter and type registers*/
1001 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1002 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1003 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1004 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1005
ptrauth_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1006 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1007 const struct sys_reg_desc *rd)
1008 {
1009 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1010 }
1011
1012 /*
1013 * If we land here on a PtrAuth access, that is because we didn't
1014 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1015 * way this happens is when the guest does not have PtrAuth support
1016 * enabled.
1017 */
1018 #define __PTRAUTH_KEY(k) \
1019 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1020 .visibility = ptrauth_visibility}
1021
1022 #define PTRAUTH_KEY(k) \
1023 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1024 __PTRAUTH_KEY(k ## KEYHI_EL1)
1025
access_arch_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1026 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1027 struct sys_reg_params *p,
1028 const struct sys_reg_desc *r)
1029 {
1030 enum kvm_arch_timers tmr;
1031 enum kvm_arch_timer_regs treg;
1032 u64 reg = reg_to_encoding(r);
1033
1034 switch (reg) {
1035 case SYS_CNTP_TVAL_EL0:
1036 case SYS_AARCH32_CNTP_TVAL:
1037 tmr = TIMER_PTIMER;
1038 treg = TIMER_REG_TVAL;
1039 break;
1040 case SYS_CNTP_CTL_EL0:
1041 case SYS_AARCH32_CNTP_CTL:
1042 tmr = TIMER_PTIMER;
1043 treg = TIMER_REG_CTL;
1044 break;
1045 case SYS_CNTP_CVAL_EL0:
1046 case SYS_AARCH32_CNTP_CVAL:
1047 tmr = TIMER_PTIMER;
1048 treg = TIMER_REG_CVAL;
1049 break;
1050 default:
1051 BUG();
1052 }
1053
1054 if (p->is_write)
1055 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1056 else
1057 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1058
1059 return true;
1060 }
1061
1062 /* Read a sanitised cpufeature ID register by sys_reg_desc */
read_id_reg(const struct kvm_vcpu * vcpu,struct sys_reg_desc const * r,bool raz)1063 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1064 struct sys_reg_desc const *r, bool raz)
1065 {
1066 u32 id = reg_to_encoding(r);
1067 u64 val;
1068
1069 if (raz)
1070 return 0;
1071
1072 val = read_sanitised_ftr_reg(id);
1073
1074 switch (id) {
1075 case SYS_ID_AA64PFR0_EL1:
1076 if (!vcpu_has_sve(vcpu))
1077 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
1078 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU);
1079 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2);
1080 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
1081 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3);
1082 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
1083 if (irqchip_in_kernel(vcpu->kvm) &&
1084 vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
1085 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC);
1086 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1);
1087 }
1088 break;
1089 case SYS_ID_AA64PFR1_EL1:
1090 if (!kvm_has_mte(vcpu->kvm))
1091 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
1092 break;
1093 case SYS_ID_AA64ISAR1_EL1:
1094 if (!vcpu_has_ptrauth(vcpu))
1095 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) |
1096 ARM64_FEATURE_MASK(ID_AA64ISAR1_API) |
1097 ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) |
1098 ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI));
1099 break;
1100 case SYS_ID_AA64DFR0_EL1:
1101 /* Limit debug to ARMv8.0 */
1102 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER);
1103 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6);
1104 /* Limit guests to PMUv3 for ARMv8.4 */
1105 val = cpuid_feature_cap_perfmon_field(val,
1106 ID_AA64DFR0_PMUVER_SHIFT,
1107 kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
1108 /* Hide SPE from guests */
1109 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER);
1110 break;
1111 case SYS_ID_DFR0_EL1:
1112 /* Limit guests to PMUv3 for ARMv8.4 */
1113 val = cpuid_feature_cap_perfmon_field(val,
1114 ID_DFR0_PERFMON_SHIFT,
1115 kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
1116 break;
1117 }
1118
1119 return val;
1120 }
1121
id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1122 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1123 const struct sys_reg_desc *r)
1124 {
1125 u32 id = reg_to_encoding(r);
1126
1127 switch (id) {
1128 case SYS_ID_AA64ZFR0_EL1:
1129 if (!vcpu_has_sve(vcpu))
1130 return REG_RAZ;
1131 break;
1132 }
1133
1134 return 0;
1135 }
1136
1137 /* cpufeature ID register access trap handlers */
1138
__access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r,bool raz)1139 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1140 struct sys_reg_params *p,
1141 const struct sys_reg_desc *r,
1142 bool raz)
1143 {
1144 if (p->is_write)
1145 return write_to_read_only(vcpu, p, r);
1146
1147 p->regval = read_id_reg(vcpu, r, raz);
1148 return true;
1149 }
1150
access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1151 static bool access_id_reg(struct kvm_vcpu *vcpu,
1152 struct sys_reg_params *p,
1153 const struct sys_reg_desc *r)
1154 {
1155 bool raz = sysreg_visible_as_raz(vcpu, r);
1156
1157 return __access_id_reg(vcpu, p, r, raz);
1158 }
1159
access_raz_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1160 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1161 struct sys_reg_params *p,
1162 const struct sys_reg_desc *r)
1163 {
1164 return __access_id_reg(vcpu, p, r, true);
1165 }
1166
1167 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1168 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1169 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1170
1171 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1172 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1173 const struct sys_reg_desc *rd)
1174 {
1175 if (vcpu_has_sve(vcpu))
1176 return 0;
1177
1178 return REG_HIDDEN;
1179 }
1180
set_id_aa64pfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1181 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1182 const struct sys_reg_desc *rd,
1183 const struct kvm_one_reg *reg, void __user *uaddr)
1184 {
1185 const u64 id = sys_reg_to_index(rd);
1186 u8 csv2, csv3;
1187 int err;
1188 u64 val;
1189
1190 err = reg_from_user(&val, uaddr, id);
1191 if (err)
1192 return err;
1193
1194 /*
1195 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
1196 * it doesn't promise more than what is actually provided (the
1197 * guest could otherwise be covered in ectoplasmic residue).
1198 */
1199 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT);
1200 if (csv2 > 1 ||
1201 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
1202 return -EINVAL;
1203
1204 /* Same thing for CSV3 */
1205 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT);
1206 if (csv3 > 1 ||
1207 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
1208 return -EINVAL;
1209
1210 /* We can only differ with CSV[23], and anything else is an error */
1211 val ^= read_id_reg(vcpu, rd, false);
1212 val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) |
1213 (0xFUL << ID_AA64PFR0_CSV3_SHIFT));
1214 if (val)
1215 return -EINVAL;
1216
1217 vcpu->kvm->arch.pfr0_csv2 = csv2;
1218 vcpu->kvm->arch.pfr0_csv3 = csv3 ;
1219
1220 return 0;
1221 }
1222
1223 /*
1224 * cpufeature ID register user accessors
1225 *
1226 * For now, these registers are immutable for userspace, so no values
1227 * are stored, and for set_id_reg() we don't allow the effective value
1228 * to be changed.
1229 */
__get_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,void __user * uaddr,bool raz)1230 static int __get_id_reg(const struct kvm_vcpu *vcpu,
1231 const struct sys_reg_desc *rd, void __user *uaddr,
1232 bool raz)
1233 {
1234 const u64 id = sys_reg_to_index(rd);
1235 const u64 val = read_id_reg(vcpu, rd, raz);
1236
1237 return reg_to_user(uaddr, &val, id);
1238 }
1239
__set_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,void __user * uaddr,bool raz)1240 static int __set_id_reg(const struct kvm_vcpu *vcpu,
1241 const struct sys_reg_desc *rd, void __user *uaddr,
1242 bool raz)
1243 {
1244 const u64 id = sys_reg_to_index(rd);
1245 int err;
1246 u64 val;
1247
1248 err = reg_from_user(&val, uaddr, id);
1249 if (err)
1250 return err;
1251
1252 /* This is what we mean by invariant: you can't change it. */
1253 if (val != read_id_reg(vcpu, rd, raz))
1254 return -EINVAL;
1255
1256 return 0;
1257 }
1258
get_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1259 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1260 const struct kvm_one_reg *reg, void __user *uaddr)
1261 {
1262 bool raz = sysreg_visible_as_raz(vcpu, rd);
1263
1264 return __get_id_reg(vcpu, rd, uaddr, raz);
1265 }
1266
set_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1267 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1268 const struct kvm_one_reg *reg, void __user *uaddr)
1269 {
1270 bool raz = sysreg_visible_as_raz(vcpu, rd);
1271
1272 return __set_id_reg(vcpu, rd, uaddr, raz);
1273 }
1274
set_raz_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1275 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1276 const struct kvm_one_reg *reg, void __user *uaddr)
1277 {
1278 return __set_id_reg(vcpu, rd, uaddr, true);
1279 }
1280
get_raz_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1281 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1282 const struct kvm_one_reg *reg, void __user *uaddr)
1283 {
1284 const u64 id = sys_reg_to_index(rd);
1285 const u64 val = 0;
1286
1287 return reg_to_user(uaddr, &val, id);
1288 }
1289
set_wi_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1290 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1291 const struct kvm_one_reg *reg, void __user *uaddr)
1292 {
1293 int err;
1294 u64 val;
1295
1296 /* Perform the access even if we are going to ignore the value */
1297 err = reg_from_user(&val, uaddr, sys_reg_to_index(rd));
1298 if (err)
1299 return err;
1300
1301 return 0;
1302 }
1303
access_ctr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1304 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1305 const struct sys_reg_desc *r)
1306 {
1307 if (p->is_write)
1308 return write_to_read_only(vcpu, p, r);
1309
1310 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1311 return true;
1312 }
1313
access_clidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1314 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1315 const struct sys_reg_desc *r)
1316 {
1317 if (p->is_write)
1318 return write_to_read_only(vcpu, p, r);
1319
1320 p->regval = read_sysreg(clidr_el1);
1321 return true;
1322 }
1323
access_csselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1324 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1325 const struct sys_reg_desc *r)
1326 {
1327 int reg = r->reg;
1328
1329 if (p->is_write)
1330 vcpu_write_sys_reg(vcpu, p->regval, reg);
1331 else
1332 p->regval = vcpu_read_sys_reg(vcpu, reg);
1333 return true;
1334 }
1335
access_ccsidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1336 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1337 const struct sys_reg_desc *r)
1338 {
1339 u32 csselr;
1340
1341 if (p->is_write)
1342 return write_to_read_only(vcpu, p, r);
1343
1344 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1345 p->regval = get_ccsidr(csselr);
1346
1347 /*
1348 * Guests should not be doing cache operations by set/way at all, and
1349 * for this reason, we trap them and attempt to infer the intent, so
1350 * that we can flush the entire guest's address space at the appropriate
1351 * time.
1352 * To prevent this trapping from causing performance problems, let's
1353 * expose the geometry of all data and unified caches (which are
1354 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1355 * [If guests should attempt to infer aliasing properties from the
1356 * geometry (which is not permitted by the architecture), they would
1357 * only do so for virtually indexed caches.]
1358 */
1359 if (!(csselr & 1)) // data or unified cache
1360 p->regval &= ~GENMASK(27, 3);
1361 return true;
1362 }
1363
mte_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1364 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
1365 const struct sys_reg_desc *rd)
1366 {
1367 if (kvm_has_mte(vcpu->kvm))
1368 return 0;
1369
1370 return REG_HIDDEN;
1371 }
1372
1373 #define MTE_REG(name) { \
1374 SYS_DESC(SYS_##name), \
1375 .access = undef_access, \
1376 .reset = reset_unknown, \
1377 .reg = name, \
1378 .visibility = mte_visibility, \
1379 }
1380
1381 /* sys_reg_desc initialiser for known cpufeature ID registers */
1382 #define ID_SANITISED(name) { \
1383 SYS_DESC(SYS_##name), \
1384 .access = access_id_reg, \
1385 .get_user = get_id_reg, \
1386 .set_user = set_id_reg, \
1387 .visibility = id_visibility, \
1388 }
1389
1390 /*
1391 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1392 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1393 * (1 <= crm < 8, 0 <= Op2 < 8).
1394 */
1395 #define ID_UNALLOCATED(crm, op2) { \
1396 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1397 .access = access_raz_id_reg, \
1398 .get_user = get_raz_reg, \
1399 .set_user = set_raz_id_reg, \
1400 }
1401
1402 /*
1403 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1404 * For now, these are exposed just like unallocated ID regs: they appear
1405 * RAZ for the guest.
1406 */
1407 #define ID_HIDDEN(name) { \
1408 SYS_DESC(SYS_##name), \
1409 .access = access_raz_id_reg, \
1410 .get_user = get_raz_reg, \
1411 .set_user = set_raz_id_reg, \
1412 }
1413
1414 /*
1415 * Architected system registers.
1416 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1417 *
1418 * Debug handling: We do trap most, if not all debug related system
1419 * registers. The implementation is good enough to ensure that a guest
1420 * can use these with minimal performance degradation. The drawback is
1421 * that we don't implement any of the external debug, none of the
1422 * OSlock protocol. This should be revisited if we ever encounter a
1423 * more demanding guest...
1424 */
1425 static const struct sys_reg_desc sys_reg_descs[] = {
1426 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1427 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1428 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1429
1430 DBG_BCR_BVR_WCR_WVR_EL1(0),
1431 DBG_BCR_BVR_WCR_WVR_EL1(1),
1432 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1433 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1434 DBG_BCR_BVR_WCR_WVR_EL1(2),
1435 DBG_BCR_BVR_WCR_WVR_EL1(3),
1436 DBG_BCR_BVR_WCR_WVR_EL1(4),
1437 DBG_BCR_BVR_WCR_WVR_EL1(5),
1438 DBG_BCR_BVR_WCR_WVR_EL1(6),
1439 DBG_BCR_BVR_WCR_WVR_EL1(7),
1440 DBG_BCR_BVR_WCR_WVR_EL1(8),
1441 DBG_BCR_BVR_WCR_WVR_EL1(9),
1442 DBG_BCR_BVR_WCR_WVR_EL1(10),
1443 DBG_BCR_BVR_WCR_WVR_EL1(11),
1444 DBG_BCR_BVR_WCR_WVR_EL1(12),
1445 DBG_BCR_BVR_WCR_WVR_EL1(13),
1446 DBG_BCR_BVR_WCR_WVR_EL1(14),
1447 DBG_BCR_BVR_WCR_WVR_EL1(15),
1448
1449 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1450 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1451 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1452 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1453 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1454 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1455 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1456 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1457
1458 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1459 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1460 // DBGDTR[TR]X_EL0 share the same encoding
1461 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1462
1463 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1464
1465 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1466
1467 /*
1468 * ID regs: all ID_SANITISED() entries here must have corresponding
1469 * entries in arm64_ftr_regs[].
1470 */
1471
1472 /* AArch64 mappings of the AArch32 ID registers */
1473 /* CRm=1 */
1474 ID_SANITISED(ID_PFR0_EL1),
1475 ID_SANITISED(ID_PFR1_EL1),
1476 ID_SANITISED(ID_DFR0_EL1),
1477 ID_HIDDEN(ID_AFR0_EL1),
1478 ID_SANITISED(ID_MMFR0_EL1),
1479 ID_SANITISED(ID_MMFR1_EL1),
1480 ID_SANITISED(ID_MMFR2_EL1),
1481 ID_SANITISED(ID_MMFR3_EL1),
1482
1483 /* CRm=2 */
1484 ID_SANITISED(ID_ISAR0_EL1),
1485 ID_SANITISED(ID_ISAR1_EL1),
1486 ID_SANITISED(ID_ISAR2_EL1),
1487 ID_SANITISED(ID_ISAR3_EL1),
1488 ID_SANITISED(ID_ISAR4_EL1),
1489 ID_SANITISED(ID_ISAR5_EL1),
1490 ID_SANITISED(ID_MMFR4_EL1),
1491 ID_SANITISED(ID_ISAR6_EL1),
1492
1493 /* CRm=3 */
1494 ID_SANITISED(MVFR0_EL1),
1495 ID_SANITISED(MVFR1_EL1),
1496 ID_SANITISED(MVFR2_EL1),
1497 ID_UNALLOCATED(3,3),
1498 ID_SANITISED(ID_PFR2_EL1),
1499 ID_HIDDEN(ID_DFR1_EL1),
1500 ID_SANITISED(ID_MMFR5_EL1),
1501 ID_UNALLOCATED(3,7),
1502
1503 /* AArch64 ID registers */
1504 /* CRm=4 */
1505 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
1506 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
1507 ID_SANITISED(ID_AA64PFR1_EL1),
1508 ID_UNALLOCATED(4,2),
1509 ID_UNALLOCATED(4,3),
1510 ID_SANITISED(ID_AA64ZFR0_EL1),
1511 ID_UNALLOCATED(4,5),
1512 ID_UNALLOCATED(4,6),
1513 ID_UNALLOCATED(4,7),
1514
1515 /* CRm=5 */
1516 ID_SANITISED(ID_AA64DFR0_EL1),
1517 ID_SANITISED(ID_AA64DFR1_EL1),
1518 ID_UNALLOCATED(5,2),
1519 ID_UNALLOCATED(5,3),
1520 ID_HIDDEN(ID_AA64AFR0_EL1),
1521 ID_HIDDEN(ID_AA64AFR1_EL1),
1522 ID_UNALLOCATED(5,6),
1523 ID_UNALLOCATED(5,7),
1524
1525 /* CRm=6 */
1526 ID_SANITISED(ID_AA64ISAR0_EL1),
1527 ID_SANITISED(ID_AA64ISAR1_EL1),
1528 ID_UNALLOCATED(6,2),
1529 ID_UNALLOCATED(6,3),
1530 ID_UNALLOCATED(6,4),
1531 ID_UNALLOCATED(6,5),
1532 ID_UNALLOCATED(6,6),
1533 ID_UNALLOCATED(6,7),
1534
1535 /* CRm=7 */
1536 ID_SANITISED(ID_AA64MMFR0_EL1),
1537 ID_SANITISED(ID_AA64MMFR1_EL1),
1538 ID_SANITISED(ID_AA64MMFR2_EL1),
1539 ID_UNALLOCATED(7,3),
1540 ID_UNALLOCATED(7,4),
1541 ID_UNALLOCATED(7,5),
1542 ID_UNALLOCATED(7,6),
1543 ID_UNALLOCATED(7,7),
1544
1545 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1546 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
1547 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1548
1549 MTE_REG(RGSR_EL1),
1550 MTE_REG(GCR_EL1),
1551
1552 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1553 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
1554 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1555 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1556 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1557
1558 PTRAUTH_KEY(APIA),
1559 PTRAUTH_KEY(APIB),
1560 PTRAUTH_KEY(APDA),
1561 PTRAUTH_KEY(APDB),
1562 PTRAUTH_KEY(APGA),
1563
1564 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1565 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1566 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1567
1568 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1569 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1570 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1571 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1572 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1573 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1574 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1575 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1576
1577 MTE_REG(TFSR_EL1),
1578 MTE_REG(TFSRE0_EL1),
1579
1580 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1581 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1582
1583 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
1584 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
1585 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
1586 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
1587 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
1588 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
1589 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
1590 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
1591 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
1592 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
1593 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
1594 /* PMBIDR_EL1 is not trapped */
1595
1596 { PMU_SYS_REG(SYS_PMINTENSET_EL1),
1597 .access = access_pminten, .reg = PMINTENSET_EL1 },
1598 { PMU_SYS_REG(SYS_PMINTENCLR_EL1),
1599 .access = access_pminten, .reg = PMINTENSET_EL1 },
1600 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
1601
1602 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1603 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1604
1605 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1606 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1607 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1608 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1609 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1610
1611 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1612 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1613
1614 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1615 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1616 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1617 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1618 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1619 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1620 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1621 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1622 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1623 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1624 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1625 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1626
1627 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1628 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1629
1630 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
1631
1632 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1633
1634 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1635 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1636 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1637 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1638
1639 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr,
1640 .reset = reset_pmcr, .reg = PMCR_EL0 },
1641 { PMU_SYS_REG(SYS_PMCNTENSET_EL0),
1642 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1643 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0),
1644 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1645 { PMU_SYS_REG(SYS_PMOVSCLR_EL0),
1646 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1647 /*
1648 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
1649 * previously (and pointlessly) advertised in the past...
1650 */
1651 { PMU_SYS_REG(SYS_PMSWINC_EL0),
1652 .get_user = get_raz_reg, .set_user = set_wi_reg,
1653 .access = access_pmswinc, .reset = NULL },
1654 { PMU_SYS_REG(SYS_PMSELR_EL0),
1655 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
1656 { PMU_SYS_REG(SYS_PMCEID0_EL0),
1657 .access = access_pmceid, .reset = NULL },
1658 { PMU_SYS_REG(SYS_PMCEID1_EL0),
1659 .access = access_pmceid, .reset = NULL },
1660 { PMU_SYS_REG(SYS_PMCCNTR_EL0),
1661 .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 },
1662 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0),
1663 .access = access_pmu_evtyper, .reset = NULL },
1664 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0),
1665 .access = access_pmu_evcntr, .reset = NULL },
1666 /*
1667 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1668 * in 32bit mode. Here we choose to reset it as zero for consistency.
1669 */
1670 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr,
1671 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
1672 { PMU_SYS_REG(SYS_PMOVSSET_EL0),
1673 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1674
1675 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1676 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1677
1678 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
1679
1680 { SYS_DESC(SYS_AMCR_EL0), undef_access },
1681 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
1682 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
1683 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
1684 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
1685 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
1686 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
1687 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
1688 AMU_AMEVCNTR0_EL0(0),
1689 AMU_AMEVCNTR0_EL0(1),
1690 AMU_AMEVCNTR0_EL0(2),
1691 AMU_AMEVCNTR0_EL0(3),
1692 AMU_AMEVCNTR0_EL0(4),
1693 AMU_AMEVCNTR0_EL0(5),
1694 AMU_AMEVCNTR0_EL0(6),
1695 AMU_AMEVCNTR0_EL0(7),
1696 AMU_AMEVCNTR0_EL0(8),
1697 AMU_AMEVCNTR0_EL0(9),
1698 AMU_AMEVCNTR0_EL0(10),
1699 AMU_AMEVCNTR0_EL0(11),
1700 AMU_AMEVCNTR0_EL0(12),
1701 AMU_AMEVCNTR0_EL0(13),
1702 AMU_AMEVCNTR0_EL0(14),
1703 AMU_AMEVCNTR0_EL0(15),
1704 AMU_AMEVTYPER0_EL0(0),
1705 AMU_AMEVTYPER0_EL0(1),
1706 AMU_AMEVTYPER0_EL0(2),
1707 AMU_AMEVTYPER0_EL0(3),
1708 AMU_AMEVTYPER0_EL0(4),
1709 AMU_AMEVTYPER0_EL0(5),
1710 AMU_AMEVTYPER0_EL0(6),
1711 AMU_AMEVTYPER0_EL0(7),
1712 AMU_AMEVTYPER0_EL0(8),
1713 AMU_AMEVTYPER0_EL0(9),
1714 AMU_AMEVTYPER0_EL0(10),
1715 AMU_AMEVTYPER0_EL0(11),
1716 AMU_AMEVTYPER0_EL0(12),
1717 AMU_AMEVTYPER0_EL0(13),
1718 AMU_AMEVTYPER0_EL0(14),
1719 AMU_AMEVTYPER0_EL0(15),
1720 AMU_AMEVCNTR1_EL0(0),
1721 AMU_AMEVCNTR1_EL0(1),
1722 AMU_AMEVCNTR1_EL0(2),
1723 AMU_AMEVCNTR1_EL0(3),
1724 AMU_AMEVCNTR1_EL0(4),
1725 AMU_AMEVCNTR1_EL0(5),
1726 AMU_AMEVCNTR1_EL0(6),
1727 AMU_AMEVCNTR1_EL0(7),
1728 AMU_AMEVCNTR1_EL0(8),
1729 AMU_AMEVCNTR1_EL0(9),
1730 AMU_AMEVCNTR1_EL0(10),
1731 AMU_AMEVCNTR1_EL0(11),
1732 AMU_AMEVCNTR1_EL0(12),
1733 AMU_AMEVCNTR1_EL0(13),
1734 AMU_AMEVCNTR1_EL0(14),
1735 AMU_AMEVCNTR1_EL0(15),
1736 AMU_AMEVTYPER1_EL0(0),
1737 AMU_AMEVTYPER1_EL0(1),
1738 AMU_AMEVTYPER1_EL0(2),
1739 AMU_AMEVTYPER1_EL0(3),
1740 AMU_AMEVTYPER1_EL0(4),
1741 AMU_AMEVTYPER1_EL0(5),
1742 AMU_AMEVTYPER1_EL0(6),
1743 AMU_AMEVTYPER1_EL0(7),
1744 AMU_AMEVTYPER1_EL0(8),
1745 AMU_AMEVTYPER1_EL0(9),
1746 AMU_AMEVTYPER1_EL0(10),
1747 AMU_AMEVTYPER1_EL0(11),
1748 AMU_AMEVTYPER1_EL0(12),
1749 AMU_AMEVTYPER1_EL0(13),
1750 AMU_AMEVTYPER1_EL0(14),
1751 AMU_AMEVTYPER1_EL0(15),
1752
1753 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1754 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1755 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1756
1757 /* PMEVCNTRn_EL0 */
1758 PMU_PMEVCNTR_EL0(0),
1759 PMU_PMEVCNTR_EL0(1),
1760 PMU_PMEVCNTR_EL0(2),
1761 PMU_PMEVCNTR_EL0(3),
1762 PMU_PMEVCNTR_EL0(4),
1763 PMU_PMEVCNTR_EL0(5),
1764 PMU_PMEVCNTR_EL0(6),
1765 PMU_PMEVCNTR_EL0(7),
1766 PMU_PMEVCNTR_EL0(8),
1767 PMU_PMEVCNTR_EL0(9),
1768 PMU_PMEVCNTR_EL0(10),
1769 PMU_PMEVCNTR_EL0(11),
1770 PMU_PMEVCNTR_EL0(12),
1771 PMU_PMEVCNTR_EL0(13),
1772 PMU_PMEVCNTR_EL0(14),
1773 PMU_PMEVCNTR_EL0(15),
1774 PMU_PMEVCNTR_EL0(16),
1775 PMU_PMEVCNTR_EL0(17),
1776 PMU_PMEVCNTR_EL0(18),
1777 PMU_PMEVCNTR_EL0(19),
1778 PMU_PMEVCNTR_EL0(20),
1779 PMU_PMEVCNTR_EL0(21),
1780 PMU_PMEVCNTR_EL0(22),
1781 PMU_PMEVCNTR_EL0(23),
1782 PMU_PMEVCNTR_EL0(24),
1783 PMU_PMEVCNTR_EL0(25),
1784 PMU_PMEVCNTR_EL0(26),
1785 PMU_PMEVCNTR_EL0(27),
1786 PMU_PMEVCNTR_EL0(28),
1787 PMU_PMEVCNTR_EL0(29),
1788 PMU_PMEVCNTR_EL0(30),
1789 /* PMEVTYPERn_EL0 */
1790 PMU_PMEVTYPER_EL0(0),
1791 PMU_PMEVTYPER_EL0(1),
1792 PMU_PMEVTYPER_EL0(2),
1793 PMU_PMEVTYPER_EL0(3),
1794 PMU_PMEVTYPER_EL0(4),
1795 PMU_PMEVTYPER_EL0(5),
1796 PMU_PMEVTYPER_EL0(6),
1797 PMU_PMEVTYPER_EL0(7),
1798 PMU_PMEVTYPER_EL0(8),
1799 PMU_PMEVTYPER_EL0(9),
1800 PMU_PMEVTYPER_EL0(10),
1801 PMU_PMEVTYPER_EL0(11),
1802 PMU_PMEVTYPER_EL0(12),
1803 PMU_PMEVTYPER_EL0(13),
1804 PMU_PMEVTYPER_EL0(14),
1805 PMU_PMEVTYPER_EL0(15),
1806 PMU_PMEVTYPER_EL0(16),
1807 PMU_PMEVTYPER_EL0(17),
1808 PMU_PMEVTYPER_EL0(18),
1809 PMU_PMEVTYPER_EL0(19),
1810 PMU_PMEVTYPER_EL0(20),
1811 PMU_PMEVTYPER_EL0(21),
1812 PMU_PMEVTYPER_EL0(22),
1813 PMU_PMEVTYPER_EL0(23),
1814 PMU_PMEVTYPER_EL0(24),
1815 PMU_PMEVTYPER_EL0(25),
1816 PMU_PMEVTYPER_EL0(26),
1817 PMU_PMEVTYPER_EL0(27),
1818 PMU_PMEVTYPER_EL0(28),
1819 PMU_PMEVTYPER_EL0(29),
1820 PMU_PMEVTYPER_EL0(30),
1821 /*
1822 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1823 * in 32bit mode. Here we choose to reset it as zero for consistency.
1824 */
1825 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper,
1826 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
1827
1828 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1829 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1830 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1831 };
1832
trap_dbgdidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1833 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
1834 struct sys_reg_params *p,
1835 const struct sys_reg_desc *r)
1836 {
1837 if (p->is_write) {
1838 return ignore_write(vcpu, p);
1839 } else {
1840 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1841 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1842 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1843
1844 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1845 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1846 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1847 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12));
1848 return true;
1849 }
1850 }
1851
1852 /*
1853 * AArch32 debug register mappings
1854 *
1855 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1856 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1857 *
1858 * None of the other registers share their location, so treat them as
1859 * if they were 64bit.
1860 */
1861 #define DBG_BCR_BVR_WCR_WVR(n) \
1862 /* DBGBVRn */ \
1863 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1864 /* DBGBCRn */ \
1865 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1866 /* DBGWVRn */ \
1867 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1868 /* DBGWCRn */ \
1869 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1870
1871 #define DBGBXVR(n) \
1872 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
1873
1874 /*
1875 * Trapped cp14 registers. We generally ignore most of the external
1876 * debug, on the principle that they don't really make sense to a
1877 * guest. Revisit this one day, would this principle change.
1878 */
1879 static const struct sys_reg_desc cp14_regs[] = {
1880 /* DBGDIDR */
1881 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
1882 /* DBGDTRRXext */
1883 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1884
1885 DBG_BCR_BVR_WCR_WVR(0),
1886 /* DBGDSCRint */
1887 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1888 DBG_BCR_BVR_WCR_WVR(1),
1889 /* DBGDCCINT */
1890 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
1891 /* DBGDSCRext */
1892 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
1893 DBG_BCR_BVR_WCR_WVR(2),
1894 /* DBGDTR[RT]Xint */
1895 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1896 /* DBGDTR[RT]Xext */
1897 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1898 DBG_BCR_BVR_WCR_WVR(3),
1899 DBG_BCR_BVR_WCR_WVR(4),
1900 DBG_BCR_BVR_WCR_WVR(5),
1901 /* DBGWFAR */
1902 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1903 /* DBGOSECCR */
1904 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1905 DBG_BCR_BVR_WCR_WVR(6),
1906 /* DBGVCR */
1907 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
1908 DBG_BCR_BVR_WCR_WVR(7),
1909 DBG_BCR_BVR_WCR_WVR(8),
1910 DBG_BCR_BVR_WCR_WVR(9),
1911 DBG_BCR_BVR_WCR_WVR(10),
1912 DBG_BCR_BVR_WCR_WVR(11),
1913 DBG_BCR_BVR_WCR_WVR(12),
1914 DBG_BCR_BVR_WCR_WVR(13),
1915 DBG_BCR_BVR_WCR_WVR(14),
1916 DBG_BCR_BVR_WCR_WVR(15),
1917
1918 /* DBGDRAR (32bit) */
1919 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1920
1921 DBGBXVR(0),
1922 /* DBGOSLAR */
1923 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1924 DBGBXVR(1),
1925 /* DBGOSLSR */
1926 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1927 DBGBXVR(2),
1928 DBGBXVR(3),
1929 /* DBGOSDLR */
1930 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1931 DBGBXVR(4),
1932 /* DBGPRCR */
1933 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1934 DBGBXVR(5),
1935 DBGBXVR(6),
1936 DBGBXVR(7),
1937 DBGBXVR(8),
1938 DBGBXVR(9),
1939 DBGBXVR(10),
1940 DBGBXVR(11),
1941 DBGBXVR(12),
1942 DBGBXVR(13),
1943 DBGBXVR(14),
1944 DBGBXVR(15),
1945
1946 /* DBGDSAR (32bit) */
1947 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1948
1949 /* DBGDEVID2 */
1950 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1951 /* DBGDEVID1 */
1952 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1953 /* DBGDEVID */
1954 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1955 /* DBGCLAIMSET */
1956 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1957 /* DBGCLAIMCLR */
1958 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1959 /* DBGAUTHSTATUS */
1960 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1961 };
1962
1963 /* Trapped cp14 64bit registers */
1964 static const struct sys_reg_desc cp14_64_regs[] = {
1965 /* DBGDRAR (64bit) */
1966 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1967
1968 /* DBGDSAR (64bit) */
1969 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1970 };
1971
1972 /* Macro to expand the PMEVCNTRn register */
1973 #define PMU_PMEVCNTR(n) \
1974 /* PMEVCNTRn */ \
1975 { Op1(0), CRn(0b1110), \
1976 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1977 access_pmu_evcntr }
1978
1979 /* Macro to expand the PMEVTYPERn register */
1980 #define PMU_PMEVTYPER(n) \
1981 /* PMEVTYPERn */ \
1982 { Op1(0), CRn(0b1110), \
1983 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1984 access_pmu_evtyper }
1985
1986 /*
1987 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1988 * depending on the way they are accessed (as a 32bit or a 64bit
1989 * register).
1990 */
1991 static const struct sys_reg_desc cp15_regs[] = {
1992 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1993 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
1994 /* ACTLR */
1995 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
1996 /* ACTLR2 */
1997 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
1998 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
1999 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
2000 /* TTBCR */
2001 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
2002 /* TTBCR2 */
2003 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
2004 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
2005 /* DFSR */
2006 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
2007 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
2008 /* ADFSR */
2009 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
2010 /* AIFSR */
2011 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
2012 /* DFAR */
2013 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
2014 /* IFAR */
2015 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
2016
2017 /*
2018 * DC{C,I,CI}SW operations:
2019 */
2020 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2021 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2022 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2023
2024 /* PMU */
2025 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
2026 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
2027 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
2028 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
2029 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
2030 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
2031 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
2032 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
2033 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
2034 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
2035 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
2036 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
2037 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
2038 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
2039 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
2040 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid },
2041 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid },
2042 /* PMMIR */
2043 { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi },
2044
2045 /* PRRR/MAIR0 */
2046 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2047 /* NMRR/MAIR1 */
2048 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2049 /* AMAIR0 */
2050 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2051 /* AMAIR1 */
2052 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2053
2054 /* ICC_SRE */
2055 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2056
2057 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2058
2059 /* Arch Tmers */
2060 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2061 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2062
2063 /* PMEVCNTRn */
2064 PMU_PMEVCNTR(0),
2065 PMU_PMEVCNTR(1),
2066 PMU_PMEVCNTR(2),
2067 PMU_PMEVCNTR(3),
2068 PMU_PMEVCNTR(4),
2069 PMU_PMEVCNTR(5),
2070 PMU_PMEVCNTR(6),
2071 PMU_PMEVCNTR(7),
2072 PMU_PMEVCNTR(8),
2073 PMU_PMEVCNTR(9),
2074 PMU_PMEVCNTR(10),
2075 PMU_PMEVCNTR(11),
2076 PMU_PMEVCNTR(12),
2077 PMU_PMEVCNTR(13),
2078 PMU_PMEVCNTR(14),
2079 PMU_PMEVCNTR(15),
2080 PMU_PMEVCNTR(16),
2081 PMU_PMEVCNTR(17),
2082 PMU_PMEVCNTR(18),
2083 PMU_PMEVCNTR(19),
2084 PMU_PMEVCNTR(20),
2085 PMU_PMEVCNTR(21),
2086 PMU_PMEVCNTR(22),
2087 PMU_PMEVCNTR(23),
2088 PMU_PMEVCNTR(24),
2089 PMU_PMEVCNTR(25),
2090 PMU_PMEVCNTR(26),
2091 PMU_PMEVCNTR(27),
2092 PMU_PMEVCNTR(28),
2093 PMU_PMEVCNTR(29),
2094 PMU_PMEVCNTR(30),
2095 /* PMEVTYPERn */
2096 PMU_PMEVTYPER(0),
2097 PMU_PMEVTYPER(1),
2098 PMU_PMEVTYPER(2),
2099 PMU_PMEVTYPER(3),
2100 PMU_PMEVTYPER(4),
2101 PMU_PMEVTYPER(5),
2102 PMU_PMEVTYPER(6),
2103 PMU_PMEVTYPER(7),
2104 PMU_PMEVTYPER(8),
2105 PMU_PMEVTYPER(9),
2106 PMU_PMEVTYPER(10),
2107 PMU_PMEVTYPER(11),
2108 PMU_PMEVTYPER(12),
2109 PMU_PMEVTYPER(13),
2110 PMU_PMEVTYPER(14),
2111 PMU_PMEVTYPER(15),
2112 PMU_PMEVTYPER(16),
2113 PMU_PMEVTYPER(17),
2114 PMU_PMEVTYPER(18),
2115 PMU_PMEVTYPER(19),
2116 PMU_PMEVTYPER(20),
2117 PMU_PMEVTYPER(21),
2118 PMU_PMEVTYPER(22),
2119 PMU_PMEVTYPER(23),
2120 PMU_PMEVTYPER(24),
2121 PMU_PMEVTYPER(25),
2122 PMU_PMEVTYPER(26),
2123 PMU_PMEVTYPER(27),
2124 PMU_PMEVTYPER(28),
2125 PMU_PMEVTYPER(29),
2126 PMU_PMEVTYPER(30),
2127 /* PMCCFILTR */
2128 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
2129
2130 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2131 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2132 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2133 };
2134
2135 static const struct sys_reg_desc cp15_64_regs[] = {
2136 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2137 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
2138 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2139 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2140 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2141 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2142 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
2143 };
2144
check_sysreg_table(const struct sys_reg_desc * table,unsigned int n,bool is_32)2145 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2146 bool is_32)
2147 {
2148 unsigned int i;
2149
2150 for (i = 0; i < n; i++) {
2151 if (!is_32 && table[i].reg && !table[i].reset) {
2152 kvm_err("sys_reg table %p entry %d has lacks reset\n",
2153 table, i);
2154 return 1;
2155 }
2156
2157 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2158 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2159 return 1;
2160 }
2161 }
2162
2163 return 0;
2164 }
2165
kvm_handle_cp14_load_store(struct kvm_vcpu * vcpu)2166 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
2167 {
2168 kvm_inject_undefined(vcpu);
2169 return 1;
2170 }
2171
perform_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)2172 static void perform_access(struct kvm_vcpu *vcpu,
2173 struct sys_reg_params *params,
2174 const struct sys_reg_desc *r)
2175 {
2176 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2177
2178 /* Check for regs disabled by runtime config */
2179 if (sysreg_hidden(vcpu, r)) {
2180 kvm_inject_undefined(vcpu);
2181 return;
2182 }
2183
2184 /*
2185 * Not having an accessor means that we have configured a trap
2186 * that we don't know how to handle. This certainly qualifies
2187 * as a gross bug that should be fixed right away.
2188 */
2189 BUG_ON(!r->access);
2190
2191 /* Skip instruction if instructed so */
2192 if (likely(r->access(vcpu, params, r)))
2193 kvm_incr_pc(vcpu);
2194 }
2195
2196 /*
2197 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2198 * call the corresponding trap handler.
2199 *
2200 * @params: pointer to the descriptor of the access
2201 * @table: array of trap descriptors
2202 * @num: size of the trap descriptor array
2203 *
2204 * Return 0 if the access has been handled, and -1 if not.
2205 */
emulate_cp(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * table,size_t num)2206 static int emulate_cp(struct kvm_vcpu *vcpu,
2207 struct sys_reg_params *params,
2208 const struct sys_reg_desc *table,
2209 size_t num)
2210 {
2211 const struct sys_reg_desc *r;
2212
2213 if (!table)
2214 return -1; /* Not handled */
2215
2216 r = find_reg(params, table, num);
2217
2218 if (r) {
2219 perform_access(vcpu, params, r);
2220 return 0;
2221 }
2222
2223 /* Not handled */
2224 return -1;
2225 }
2226
unhandled_cp_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2227 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2228 struct sys_reg_params *params)
2229 {
2230 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
2231 int cp = -1;
2232
2233 switch (esr_ec) {
2234 case ESR_ELx_EC_CP15_32:
2235 case ESR_ELx_EC_CP15_64:
2236 cp = 15;
2237 break;
2238 case ESR_ELx_EC_CP14_MR:
2239 case ESR_ELx_EC_CP14_64:
2240 cp = 14;
2241 break;
2242 default:
2243 WARN_ON(1);
2244 }
2245
2246 print_sys_reg_msg(params,
2247 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2248 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2249 kvm_inject_undefined(vcpu);
2250 }
2251
2252 /**
2253 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2254 * @vcpu: The VCPU pointer
2255 * @run: The kvm_run struct
2256 */
kvm_handle_cp_64(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)2257 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2258 const struct sys_reg_desc *global,
2259 size_t nr_global)
2260 {
2261 struct sys_reg_params params;
2262 u32 esr = kvm_vcpu_get_esr(vcpu);
2263 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2264 int Rt2 = (esr >> 10) & 0x1f;
2265
2266 params.CRm = (esr >> 1) & 0xf;
2267 params.is_write = ((esr & 1) == 0);
2268
2269 params.Op0 = 0;
2270 params.Op1 = (esr >> 16) & 0xf;
2271 params.Op2 = 0;
2272 params.CRn = 0;
2273
2274 /*
2275 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2276 * backends between AArch32 and AArch64, we get away with it.
2277 */
2278 if (params.is_write) {
2279 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2280 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2281 }
2282
2283 /*
2284 * If the table contains a handler, handle the
2285 * potential register operation in the case of a read and return
2286 * with success.
2287 */
2288 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
2289 /* Split up the value between registers for the read side */
2290 if (!params.is_write) {
2291 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2292 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2293 }
2294
2295 return 1;
2296 }
2297
2298 unhandled_cp_access(vcpu, ¶ms);
2299 return 1;
2300 }
2301
2302 /**
2303 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2304 * @vcpu: The VCPU pointer
2305 * @run: The kvm_run struct
2306 */
kvm_handle_cp_32(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)2307 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2308 const struct sys_reg_desc *global,
2309 size_t nr_global)
2310 {
2311 struct sys_reg_params params;
2312 u32 esr = kvm_vcpu_get_esr(vcpu);
2313 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2314
2315 params.CRm = (esr >> 1) & 0xf;
2316 params.regval = vcpu_get_reg(vcpu, Rt);
2317 params.is_write = ((esr & 1) == 0);
2318 params.CRn = (esr >> 10) & 0xf;
2319 params.Op0 = 0;
2320 params.Op1 = (esr >> 14) & 0x7;
2321 params.Op2 = (esr >> 17) & 0x7;
2322
2323 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
2324 if (!params.is_write)
2325 vcpu_set_reg(vcpu, Rt, params.regval);
2326 return 1;
2327 }
2328
2329 unhandled_cp_access(vcpu, ¶ms);
2330 return 1;
2331 }
2332
kvm_handle_cp15_64(struct kvm_vcpu * vcpu)2333 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
2334 {
2335 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
2336 }
2337
kvm_handle_cp15_32(struct kvm_vcpu * vcpu)2338 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
2339 {
2340 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
2341 }
2342
kvm_handle_cp14_64(struct kvm_vcpu * vcpu)2343 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
2344 {
2345 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
2346 }
2347
kvm_handle_cp14_32(struct kvm_vcpu * vcpu)2348 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
2349 {
2350 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs));
2351 }
2352
is_imp_def_sys_reg(struct sys_reg_params * params)2353 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2354 {
2355 // See ARM DDI 0487E.a, section D12.3.2
2356 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2357 }
2358
emulate_sys_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2359 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2360 struct sys_reg_params *params)
2361 {
2362 const struct sys_reg_desc *r;
2363
2364 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2365
2366 if (likely(r)) {
2367 perform_access(vcpu, params, r);
2368 } else if (is_imp_def_sys_reg(params)) {
2369 kvm_inject_undefined(vcpu);
2370 } else {
2371 print_sys_reg_msg(params,
2372 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2373 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2374 kvm_inject_undefined(vcpu);
2375 }
2376 return 1;
2377 }
2378
2379 /**
2380 * kvm_reset_sys_regs - sets system registers to reset value
2381 * @vcpu: The VCPU pointer
2382 *
2383 * This function finds the right table above and sets the registers on the
2384 * virtual CPU struct to their architecturally defined reset values.
2385 */
kvm_reset_sys_regs(struct kvm_vcpu * vcpu)2386 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2387 {
2388 unsigned long i;
2389
2390 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2391 if (sys_reg_descs[i].reset)
2392 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
2393 }
2394
2395 /**
2396 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2397 * @vcpu: The VCPU pointer
2398 */
kvm_handle_sys_reg(struct kvm_vcpu * vcpu)2399 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
2400 {
2401 struct sys_reg_params params;
2402 unsigned long esr = kvm_vcpu_get_esr(vcpu);
2403 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2404 int ret;
2405
2406 trace_kvm_handle_sys_reg(esr);
2407
2408 params = esr_sys64_to_params(esr);
2409 params.regval = vcpu_get_reg(vcpu, Rt);
2410
2411 ret = emulate_sys_reg(vcpu, ¶ms);
2412
2413 if (!params.is_write)
2414 vcpu_set_reg(vcpu, Rt, params.regval);
2415 return ret;
2416 }
2417
2418 /******************************************************************************
2419 * Userspace API
2420 *****************************************************************************/
2421
index_to_params(u64 id,struct sys_reg_params * params)2422 static bool index_to_params(u64 id, struct sys_reg_params *params)
2423 {
2424 switch (id & KVM_REG_SIZE_MASK) {
2425 case KVM_REG_SIZE_U64:
2426 /* Any unused index bits means it's not valid. */
2427 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2428 | KVM_REG_ARM_COPROC_MASK
2429 | KVM_REG_ARM64_SYSREG_OP0_MASK
2430 | KVM_REG_ARM64_SYSREG_OP1_MASK
2431 | KVM_REG_ARM64_SYSREG_CRN_MASK
2432 | KVM_REG_ARM64_SYSREG_CRM_MASK
2433 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2434 return false;
2435 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2436 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2437 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2438 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2439 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2440 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2441 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2442 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2443 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2444 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2445 return true;
2446 default:
2447 return false;
2448 }
2449 }
2450
find_reg_by_id(u64 id,struct sys_reg_params * params,const struct sys_reg_desc table[],unsigned int num)2451 const struct sys_reg_desc *find_reg_by_id(u64 id,
2452 struct sys_reg_params *params,
2453 const struct sys_reg_desc table[],
2454 unsigned int num)
2455 {
2456 if (!index_to_params(id, params))
2457 return NULL;
2458
2459 return find_reg(params, table, num);
2460 }
2461
2462 /* Decode an index value, and find the sys_reg_desc entry. */
index_to_sys_reg_desc(struct kvm_vcpu * vcpu,u64 id)2463 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2464 u64 id)
2465 {
2466 const struct sys_reg_desc *r;
2467 struct sys_reg_params params;
2468
2469 /* We only do sys_reg for now. */
2470 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2471 return NULL;
2472
2473 if (!index_to_params(id, ¶ms))
2474 return NULL;
2475
2476 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2477
2478 /* Not saved in the sys_reg array and not otherwise accessible? */
2479 if (r && !(r->reg || r->get_user))
2480 r = NULL;
2481
2482 return r;
2483 }
2484
2485 /*
2486 * These are the invariant sys_reg registers: we let the guest see the
2487 * host versions of these, so they're part of the guest state.
2488 *
2489 * A future CPU may provide a mechanism to present different values to
2490 * the guest, or a future kvm may trap them.
2491 */
2492
2493 #define FUNCTION_INVARIANT(reg) \
2494 static void get_##reg(struct kvm_vcpu *v, \
2495 const struct sys_reg_desc *r) \
2496 { \
2497 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2498 }
2499
2500 FUNCTION_INVARIANT(midr_el1)
FUNCTION_INVARIANT(revidr_el1)2501 FUNCTION_INVARIANT(revidr_el1)
2502 FUNCTION_INVARIANT(clidr_el1)
2503 FUNCTION_INVARIANT(aidr_el1)
2504
2505 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2506 {
2507 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2508 }
2509
2510 /* ->val is filled in by kvm_sys_reg_table_init() */
2511 static struct sys_reg_desc invariant_sys_regs[] = {
2512 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2513 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2514 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2515 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2516 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2517 };
2518
reg_from_user(u64 * val,const void __user * uaddr,u64 id)2519 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2520 {
2521 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2522 return -EFAULT;
2523 return 0;
2524 }
2525
reg_to_user(void __user * uaddr,const u64 * val,u64 id)2526 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2527 {
2528 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2529 return -EFAULT;
2530 return 0;
2531 }
2532
get_invariant_sys_reg(u64 id,void __user * uaddr)2533 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2534 {
2535 struct sys_reg_params params;
2536 const struct sys_reg_desc *r;
2537
2538 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2539 ARRAY_SIZE(invariant_sys_regs));
2540 if (!r)
2541 return -ENOENT;
2542
2543 return reg_to_user(uaddr, &r->val, id);
2544 }
2545
set_invariant_sys_reg(u64 id,void __user * uaddr)2546 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2547 {
2548 struct sys_reg_params params;
2549 const struct sys_reg_desc *r;
2550 int err;
2551 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2552
2553 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2554 ARRAY_SIZE(invariant_sys_regs));
2555 if (!r)
2556 return -ENOENT;
2557
2558 err = reg_from_user(&val, uaddr, id);
2559 if (err)
2560 return err;
2561
2562 /* This is what we mean by invariant: you can't change it. */
2563 if (r->val != val)
2564 return -EINVAL;
2565
2566 return 0;
2567 }
2568
is_valid_cache(u32 val)2569 static bool is_valid_cache(u32 val)
2570 {
2571 u32 level, ctype;
2572
2573 if (val >= CSSELR_MAX)
2574 return false;
2575
2576 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2577 level = (val >> 1);
2578 ctype = (cache_levels >> (level * 3)) & 7;
2579
2580 switch (ctype) {
2581 case 0: /* No cache */
2582 return false;
2583 case 1: /* Instruction cache only */
2584 return (val & 1);
2585 case 2: /* Data cache only */
2586 case 4: /* Unified cache */
2587 return !(val & 1);
2588 case 3: /* Separate instruction and data caches */
2589 return true;
2590 default: /* Reserved: we can't know instruction or data. */
2591 return false;
2592 }
2593 }
2594
demux_c15_get(u64 id,void __user * uaddr)2595 static int demux_c15_get(u64 id, void __user *uaddr)
2596 {
2597 u32 val;
2598 u32 __user *uval = uaddr;
2599
2600 /* Fail if we have unknown bits set. */
2601 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2602 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2603 return -ENOENT;
2604
2605 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2606 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2607 if (KVM_REG_SIZE(id) != 4)
2608 return -ENOENT;
2609 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2610 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2611 if (!is_valid_cache(val))
2612 return -ENOENT;
2613
2614 return put_user(get_ccsidr(val), uval);
2615 default:
2616 return -ENOENT;
2617 }
2618 }
2619
demux_c15_set(u64 id,void __user * uaddr)2620 static int demux_c15_set(u64 id, void __user *uaddr)
2621 {
2622 u32 val, newval;
2623 u32 __user *uval = uaddr;
2624
2625 /* Fail if we have unknown bits set. */
2626 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2627 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2628 return -ENOENT;
2629
2630 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2631 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2632 if (KVM_REG_SIZE(id) != 4)
2633 return -ENOENT;
2634 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2635 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2636 if (!is_valid_cache(val))
2637 return -ENOENT;
2638
2639 if (get_user(newval, uval))
2640 return -EFAULT;
2641
2642 /* This is also invariant: you can't change it. */
2643 if (newval != get_ccsidr(val))
2644 return -EINVAL;
2645 return 0;
2646 default:
2647 return -ENOENT;
2648 }
2649 }
2650
kvm_arm_sys_reg_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)2651 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2652 {
2653 const struct sys_reg_desc *r;
2654 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2655
2656 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2657 return demux_c15_get(reg->id, uaddr);
2658
2659 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2660 return -ENOENT;
2661
2662 r = index_to_sys_reg_desc(vcpu, reg->id);
2663 if (!r)
2664 return get_invariant_sys_reg(reg->id, uaddr);
2665
2666 /* Check for regs disabled by runtime config */
2667 if (sysreg_hidden(vcpu, r))
2668 return -ENOENT;
2669
2670 if (r->get_user)
2671 return (r->get_user)(vcpu, r, reg, uaddr);
2672
2673 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2674 }
2675
kvm_arm_sys_reg_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)2676 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2677 {
2678 const struct sys_reg_desc *r;
2679 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2680
2681 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2682 return demux_c15_set(reg->id, uaddr);
2683
2684 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2685 return -ENOENT;
2686
2687 r = index_to_sys_reg_desc(vcpu, reg->id);
2688 if (!r)
2689 return set_invariant_sys_reg(reg->id, uaddr);
2690
2691 /* Check for regs disabled by runtime config */
2692 if (sysreg_hidden(vcpu, r))
2693 return -ENOENT;
2694
2695 if (r->set_user)
2696 return (r->set_user)(vcpu, r, reg, uaddr);
2697
2698 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2699 }
2700
num_demux_regs(void)2701 static unsigned int num_demux_regs(void)
2702 {
2703 unsigned int i, count = 0;
2704
2705 for (i = 0; i < CSSELR_MAX; i++)
2706 if (is_valid_cache(i))
2707 count++;
2708
2709 return count;
2710 }
2711
write_demux_regids(u64 __user * uindices)2712 static int write_demux_regids(u64 __user *uindices)
2713 {
2714 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2715 unsigned int i;
2716
2717 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2718 for (i = 0; i < CSSELR_MAX; i++) {
2719 if (!is_valid_cache(i))
2720 continue;
2721 if (put_user(val | i, uindices))
2722 return -EFAULT;
2723 uindices++;
2724 }
2725 return 0;
2726 }
2727
sys_reg_to_index(const struct sys_reg_desc * reg)2728 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2729 {
2730 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2731 KVM_REG_ARM64_SYSREG |
2732 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2733 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2734 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2735 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2736 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2737 }
2738
copy_reg_to_user(const struct sys_reg_desc * reg,u64 __user ** uind)2739 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2740 {
2741 if (!*uind)
2742 return true;
2743
2744 if (put_user(sys_reg_to_index(reg), *uind))
2745 return false;
2746
2747 (*uind)++;
2748 return true;
2749 }
2750
walk_one_sys_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 __user ** uind,unsigned int * total)2751 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2752 const struct sys_reg_desc *rd,
2753 u64 __user **uind,
2754 unsigned int *total)
2755 {
2756 /*
2757 * Ignore registers we trap but don't save,
2758 * and for which no custom user accessor is provided.
2759 */
2760 if (!(rd->reg || rd->get_user))
2761 return 0;
2762
2763 if (sysreg_hidden(vcpu, rd))
2764 return 0;
2765
2766 if (!copy_reg_to_user(rd, uind))
2767 return -EFAULT;
2768
2769 (*total)++;
2770 return 0;
2771 }
2772
2773 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu * vcpu,u64 __user * uind)2774 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2775 {
2776 const struct sys_reg_desc *i2, *end2;
2777 unsigned int total = 0;
2778 int err;
2779
2780 i2 = sys_reg_descs;
2781 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2782
2783 while (i2 != end2) {
2784 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
2785 if (err)
2786 return err;
2787 }
2788 return total;
2789 }
2790
kvm_arm_num_sys_reg_descs(struct kvm_vcpu * vcpu)2791 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2792 {
2793 return ARRAY_SIZE(invariant_sys_regs)
2794 + num_demux_regs()
2795 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2796 }
2797
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu * vcpu,u64 __user * uindices)2798 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2799 {
2800 unsigned int i;
2801 int err;
2802
2803 /* Then give them all the invariant registers' indices. */
2804 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2805 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2806 return -EFAULT;
2807 uindices++;
2808 }
2809
2810 err = walk_sys_regs(vcpu, uindices);
2811 if (err < 0)
2812 return err;
2813 uindices += err;
2814
2815 return write_demux_regids(uindices);
2816 }
2817
kvm_sys_reg_table_init(void)2818 void kvm_sys_reg_table_init(void)
2819 {
2820 unsigned int i;
2821 struct sys_reg_desc clidr;
2822
2823 /* Make sure tables are unique and in order. */
2824 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false));
2825 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true));
2826 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true));
2827 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true));
2828 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true));
2829 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false));
2830
2831 /* We abuse the reset function to overwrite the table itself. */
2832 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2833 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2834
2835 /*
2836 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2837 *
2838 * If software reads the Cache Type fields from Ctype1
2839 * upwards, once it has seen a value of 0b000, no caches
2840 * exist at further-out levels of the hierarchy. So, for
2841 * example, if Ctype3 is the first Cache Type field with a
2842 * value of 0b000, the values of Ctype4 to Ctype7 must be
2843 * ignored.
2844 */
2845 get_clidr_el1(NULL, &clidr); /* Ugly... */
2846 cache_levels = clidr.val;
2847 for (i = 0; i < 7; i++)
2848 if (((cache_levels >> (i*3)) & 7) == 0)
2849 break;
2850 /* Clear all higher bits. */
2851 cache_levels &= (1 << (i*3))-1;
2852 }
2853